转——ESPIER Cyclone IV学习板使用之时钟建模

Diabloa · 发表于 2019-5-6 10:10

EDA365欢迎您登录！

您需要登录才可以下载或查看，没有帐号？注册

x

转——ESPIER Cyclone IV学习板使用之时钟建模

这次再设计秒表的时候无意中发现的几个问题，设计者在提供的原理图中并没有严格说明，有些参数不明确容易出问题！
这次主要问题有二，首先是数码管是共阴还是共阳没有说明或者型号说明，结果就悲剧了，第一次显示乱七八糟的！

其次是数码管编号一般是地位对应于低位使能信号，结果由于自己在设置引脚的时候经期中两个引脚设置错了，再加上自己的习惯EN【0】为最低位，结果偏偏是在最高位（左边）结果就悲剧了显示出来的真的是四不像啊！

      注：本模块设计的验证平台为：ESPIER助学行动第二期FPGA学习板，主控芯片为ALTERA Cyclone IV之EP4CE6E22C8N，数码管为四位八段式红光高亮共阴型！
      以下为具体建模过程：
      首先展示出来的是顶层设计模块：
      module SG(clock,resetn,data,en,clk1,clk2);

input clock;
input resetn;
output wire [7:0] data;
output wire [3:0] en;
output wire clk1,clk2; //mid_signal test output port!
assign clk1=clk_dis; //10k
assign clk2=clk_sec; //1HZ
wire clk_sec;
wire clk_dis;
clock_div_module clock_div( .clock(clock),
.resetn(resetn),
.clk_0(clk_dis), //10KHZ
.clk_1(clk_sec)); //1  HZ

wire [5:0] second;
counter sec_cnt( .in(clk_sec),
.rstn(resetn),
.data(second));
reg clk_min;
always @(posedge clk_sec)
begin
if(second==6'd59)
clk_min=1'b1;
else
clk_min=1'b0;
end

wire [5:0] minute;
counter min_cnt( .in(clk_min),
.rstn(resetn),
.data(minute));

wire [3:0] data_0,data_1,data_2,data_3; //seperate minute and second
data_div second_div( .clock(clock),
.data_in(second),
.data_out0(data_0),
.data_out1(data_1));

data_div minute_div( .clock(clock),
.data_in(minute),
.data_out0(data_2),
.data_out1(data_3));

display display_module( .clock(clk_dis),
.resetn(resetn),
.clk_sec(clk_sec),
.data_0(data_0),
.data_1(data_1),
.data_2(data_2),
.data_3(data_3),
.data(data),
.en(en));
//wire [7:0]dat;
//assign data=8'b0011_1111;
endmodule
接下来为时钟分频模块，本设计中是使用的学习板自带48MHZ有源晶振，具体建模过程如下：
module clock_div_module(clock,resetn,clk_0,clk_1);
input clock; //48MHZ;
input resetn; //reset signal
output reg clk_0; //output 10KHZ;
output reg clk_1; //output 1  HZ;

reg [31:0] counter0;
reg [31:0] counter1;

always @ (posedge clock or negedge resetn)
begin
if (!resetn)
counter0=32'd0;
else if(counter0<47_999)
counter0=counter0+1;
else
counter0=32'd0;
end

always @ (posedge clock or negedge resetn)
begin
if(!resetn)
clk_0=1'b0;
else
clk_0=(counter0<23_499)?0:1;

end

always @ (posedge clk_0 or negedge resetn)
begin
if (!resetn)
counter1=32'd0;
else if(counter1<999)
counter1=counter1+1;
else
counter1=32'd0;
end

always @ (posedge clock or negedge resetn)
begin
if(!resetn)
clk_1=1'b0;
else
clk_1=(counter1<499)?1'b0:1'b1;

end
endmodule
//60进制计数器模块建模：
module counter (in,rstn,data);
// input clock; //48MHZ;
input in; //1S or 1Min
input rstn;
output reg [5:0] data;

always @ (posedge in or negedge rstn)
begin
if(!rstn)
data=6'd0;
else
begin
if(data<6'd59)
data=data+1;
else
data=6'd0;
end
end

endmodule
//十进制数加权分离模块：
module data_div(clock,data_in,data_out0,data_out1);
input clock; //50MHZ
input [5:0] data_in;
output reg [3:0] data_out0,data_out1;
//data_out0........LOW
always @(posedge clock)
begin
data_out0=data_in%10;
data_out1=data_in/10;
end
endmodule

//数码管编码模块建模：
module  sg_code_module(clock,resetn,data_in,data_out);
input clock; //48MHZ;
input resetn;
input [3:0] data_in; //data in ;
output reg[7:0] data_out;//data out with coded

function [7:0] sg_convator;
input [3:0] number;
reg [7:0] temp;
begin
case (number)
4'h0 : temp  =  8'b0011_1111;
4'h1 : temp  = 8'b0000_0110;
4'h2 : temp = 8'b0101_1011;
4'h3 : temp = 8'b0100_1111;
4'h4 : temp = 8'b0110_0110;
4'h5 : temp = 8'b0110_1101;
4'h6 : temp = 8'b0111_1101;
4'h7 : temp = 8'b0000_0111;
4'h8 : temp = 8'b0111_1111;
4'h9 : temp = 8'b0110_1111;
4'ha : temp = 8'b1000_0000; //此时的a仅作特殊字符并非16进制数中的A，用于显示隔离分与秒
default : temp =8'h00;
endcase
sg_convator=temp;
end;
endfunction

always @(posedge clock or negedge resetn)
begin
if (!resetn)
data_out=8'b1111_1111;
else
data_out=sg_convator(data_in);
end

endmodule
最后是显示驱动模块：
module display(clock,resetn,clk_sec,data_0,data_1,data_2,data_3,data,en);
input clock;
input resetn;
input clk_sec;
input [3:0] data_0,data_1,data_2,data_3;
output wire [7:0] data;
output reg [3:0] en;

reg [3:0] counter;
always @(posedge clock)
begin
case(counter)
4'b0000: counter=4'b0001;
4'b0001: counter=4'b0010;
4'b0010: counter=4'b0100;
4'b0100: counter=4'b1000;
4'b1000: counter=4'b0000;
default: counter=4'b0000;
endcase;
end

reg [7:0] temp;
always @ (posedge clock)
begin
case(counter)
4'b0000: begin en<=4'b1011;temp<=data_0;end
4'b0001: begin en<=4'b1110;temp<=data_1;end
4'b0010: begin en<=4'b1101;temp<=data_2;end
4'b0100: begin en<=4'b1011;temp<=data_3;end
4'b1000:
begin
en<=4'b0111;
if(clk_sec)
temp<=4'ha;
else
temp<=4'hb;
end
default: begin en<=4'b1111;temp<=0;end
endcase;
end

sg_code_module U1( .clock(clock),
.resetn(resetn),
.data_in(temp),
.data_out(data));
endmodule

顺便展示一下脚本设置文件：‘
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.

# Quartus II: Generate Tcl File for Project
# File: SG.tcl
# Generated on: Tue Aug 13 23:06:40 2013

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "SG"]} {
puts "

roject SG is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists SG]} {
project_open -revision SG SG
} else {
project_new -revision SG SG
}
set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:30:14 AUGUST 12, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "11.0 SP1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name VERILOG_FILE source/counter.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE source/clock_div_module.v
set_global_assignment -name VERILOG_FILE source/sg_code_module.v
set_global_assignment -name VERILOG_FILE source/data_div.v
set_global_assignment -name VERILOG_FILE source/SG.v
set_global_assignment -name VERILOG_FILE source/display.v
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_24 -to clock
set_location_assignment PIN_88 -to resetn
set_location_assignment PIN_3 -to data[7]
set_location_assignment PIN_2 -to data[6]
set_location_assignment PIN_138 -to data[5]
set_location_assignment PIN_142 -to data[4]
set_location_assignment PIN_141 -to data[3]
set_location_assignment PIN_1 -to data[2]
set_location_assignment PIN_144 -to data[1]
set_location_assignment PIN_143 -to data[0]
set_location_assignment PIN_133 -to en[3]
set_location_assignment PIN_136 -to en[2]
set_location_assignment PIN_135 -to en[1]
set_location_assignment PIN_137 -to en[0]
set_location_assignment PIN_99 -to clk2
set_location_assignment PIN_98 -to clk1
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

# Commit assignments
export_assignments

# Close project
if {$need_to_close_project} {
project_close
}
}

下次再将程序完善，届时将显示分钟与小时而非现在的秒与分，但是间隔部分闪烁平率为1HZ将继续保留！

Demyar · 发表于 2019-5-6 17:18

居然有代码太棒了

帐号		自动登录	找回密码
密码			注册

转——ESPIER Cyclone IV学习板使用之时钟建模

EDA365欢迎您登录！

浏览过的版块

推荐内容 /1