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Fixed CCRs: SPB 17.2 HF054/ P; z. f4 o$ h2 z) w* f2 E
04-26-2019" f/ g9 ~+ n0 X; I' u. o
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CCRID Product ProductLevel2 Title; J1 T% X: H. J$ h- M, F0 I
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* a9 r& n# y- k4 z! @+ S. u2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
& e! F' k# D7 |& L! T2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property% b' h$ m) n I% N. p @' H; P+ K; i
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser2 R1 }$ d: s5 M o( y
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache& \1 e2 R) q4 Q% J
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name; j# q: p1 D8 w/ f9 o
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design7 ?0 }. y& d4 |$ n
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object2 C' C j1 ?( i* K3 o# m; Y% c
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas+ g3 Z Z( i8 g: P( m6 q/ g( S- M
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
, E& {+ C7 K. W) M1 O! `2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded
! M0 H& g, K8 a( N1 [, X3 ^+ v6 h, L6 Y2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off; n: G0 p5 m! q7 u. D$ @
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set# B1 A1 g- s' @. f
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
5 B, k# ~ Q+ W& \- \: Z2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements' Y3 d. x# G/ }* G' e' f
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
8 P- ]+ Y, C' Y3 N2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element: M, J8 O0 w6 n7 L [9 X2 f
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow" O _/ m! U4 f
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
/ U7 O8 q( v9 h2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code. j/ T% x0 J) n' N# g
2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016! g* c6 y( ^. i+ d
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error d+ g g4 ^! i) v, L
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
* e7 {, O: r) V. r* q$ E3 J/ C2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.' k* g: {( k/ F
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer./ }9 u7 U, y2 c: `
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
% F5 u( O7 i( R$ }" J2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations
3 ~ K; P0 C# N, {2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE') R0 G; F2 E* e6 u
2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
; U q# K/ E2 M4 b2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets
+ M) _ }$ E3 E6 ]2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
4 R+ v; }. K" l( A& J+ |+ ?' \2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias; K) z( ]* E/ d1 Y8 |% N9 D- @
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
# y# T) @6 V0 F8 D* C5 U# H2 T, g2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
1 X$ `. L( K+ J2 ^ o9 J2 ^2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components! t) Q6 O0 {/ y' X- q
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report+ I! r; x+ b) u6 h! F& n/ Q
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
) g+ N5 n4 V" X# r2 X. C- X- }# B2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window4 ~- g/ H u8 N, I# c
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update) Z0 u l9 ]0 F- V# ?$ A8 g; E7 Z
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
) p9 C9 p/ N$ [3 t( [" d2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
9 s; {. i4 |/ ]5 J& v2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
: Z$ T. k$ N9 x7 f3 m; `: `2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes$ }4 N1 u, A, W4 g5 D
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
2 W" _$ ^/ U% ^, Q5 Y2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.( o; J! f" H! N
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
e7 s3 @: ^8 y$ c3 u6 m9 {2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.- h1 ^4 y- z9 Q
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
; A, h6 U* T9 D3 B" a( L2 T1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)( ]" O6 b* s1 J2 i. |+ ~
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
: w! d f j0 l: B* c2 |1 e& X2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design: B0 t) l3 u$ Y/ {
2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas
6 v9 z0 j3 o- }$ N7 U2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice- ~9 c5 ]8 \" a* D
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
8 \. [6 O D8 a) c/ z" a/ T0 H2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden4 H8 |/ m/ L7 ~ i. G1 J1 r
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6) M# {- v) k( ?6 l2 `+ V8 O
2050674 APD PARTITION Cannot remove C-Point from a partitioned design
: [: f; ^. K1 X4 h+ T% D2068814 APD WIREBOND Bond wires cross on auto-separate
+ o, K3 K; m, s: a: i4 `1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open, u* |6 |# r0 F! g4 K5 S
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
. W7 x& G4 h3 p+ n3 `' P" u; D2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
: w6 Z" {/ U# d$ |+ @2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
! H: A8 t7 b+ ]3 c, @) K2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
$ H; @0 H5 F# j. m5 r1 |. q* g2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix) t3 N; M) Z& x+ S3 X; y- T" m
2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager. T& f* y0 u9 G. v0 g
2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
) Z! o2 O% b& d; T: D# Z2 V' P4 E2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
8 w* C: H2 R9 W4 Z2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties# v$ [5 E" e: A& z6 v% i
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
6 w1 F3 `6 L P9 [) h& ]2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
( ]4 ]9 j. G5 J2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor8 F9 ?$ ?8 U+ B2 l* T; N2 y$ a
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
9 [2 @ j' ~- `3 q/ U2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
; t* B0 @. G5 J% y6 q2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
0 o+ _' m* e4 ~8 V7 d2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
1 w+ J! d( L' X+ p7 }& h3 V2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped8 s7 K8 ]6 D+ e' h' u3 g
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties$ w, k6 ?1 W: m; q
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated% H' d/ [+ i+ S: n7 ~& Z7 W [
2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
% g* E, P# Q+ ~% G2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
" S2 R& P8 @4 r) T3 D8 ^+ _( B2038021 PSPICE FRONTENDPLUGI Bias display is not updated
: y3 P- _# V+ z( c1 I, ~: ~2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open1 z9 [) w. B7 M9 ]1 q: H
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component' P6 P/ j, T8 J5 c! S; _/ ~
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks
' M& ]0 u/ w5 z1 W+ n+ v$ o2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
7 G( g% O: p" P3 I. ~2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign! s' a+ E4 C @& e0 O+ F* X0 B/ M+ E* [) f
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
6 `8 f) a) N% I9 l, k; a, _2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'
& j- x& X3 V( H# [2 v, o2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
5 E; e" N; j$ ]( @2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
% z3 s% \7 X% w$ j! e1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error/ r8 ?9 {0 {( h. V0 d( w
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files& I6 C8 p* U' s$ E
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.
+ L, s) z) L! }1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
, y% C, I s2 z+ ?$ O" }8 Y b5 R1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
! `. d, ^2 ~+ C7 K: C2 K! x) B% p$ L2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
1 G7 A# B" r& j8 Z& w* M; K q1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping- A* D" h1 E+ S% u
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor) ]: ~) Q! o' t7 H. E
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
: [- R3 x1 s1 l& l; l3 |1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
* G2 ?" z2 Q9 X2 X( ]1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM4 Z' D$ ]0 j5 J$ w2 T. b
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range w8 I0 [9 A' O4 y5 H0 o
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.% z) K( [* R9 ^: Z
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF, I+ u- a# o5 M" D
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space" b: a* d3 Z/ {$ |
1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
* G7 {6 E5 N: p" b6 T1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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发表于 2019-5-3 15:45
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