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Fixed CCRs: SPB 17.2 HF054
+ H/ u+ j* r* r" W$ f; ?% _; O04-26-2019
! F: u# O' A$ q' f; x========================================================================================================================================================4 a8 I7 E: K1 o# L& t
CCRID Product ProductLevel2 Title2 {1 T% ?- G. O
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5 E" X$ g: v E6 L. x2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
1 M. I0 C2 {, u4 I0 `2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
( C. y4 y6 s$ N4 f1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser8 ~! y! Y& X" [$ @6 a
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache( `- B) F9 h" A8 x8 O
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name& h( S: v6 X4 [
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design- }! u" X3 k- V$ k) k5 Z: X+ ?1 m; A
2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object% W8 w7 d/ f1 Y( S
2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
$ U; @. U4 e m6 K# Z2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation$ Q$ v+ m* q; Z& J! A
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded4 ~2 |( H* ]4 _
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off3 K- [* f; S) R- m$ d1 [
2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set) P! y/ U' @$ ^4 D. c
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
8 Q7 P/ `/ e4 a, t8 W1 y0 U' @4 J" M2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements
: x! M6 ]3 P; z# J! b. f d2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
0 z3 T6 n. t0 g6 Q6 Q2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element* v( C* z) O$ E( u1 f- B
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
' T6 S2 `. j* N* E0 k0 r2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error/ N# e6 L1 m. h/ Z: U9 T
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
; F- F7 f6 n/ F7 q2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016* }# ^& z7 T& f' c: C' P6 |$ p" Y
2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
8 {! x+ ]: V; K2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets5 p9 _' k3 d& Q+ d
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
! i" |) g1 I3 G6 Z) \2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer." |' E# |2 l* {* s
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
0 q G; f6 H" z. i' Y2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations6 ^" v& P9 |% _
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
! T8 g2 B. \4 j$ Y2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill, [: P! o/ J: W
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets! U$ i& d6 o* V9 x
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
5 Q n' R9 R% l$ d1 b* x! u2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias) g. @5 k% _0 u3 Q) |3 J
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
+ |( j L ^$ c9 d) L- H2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
+ s* H) K0 C$ X7 k2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components, }, `2 c' v# y/ w: d
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
5 ?" `- w( E/ `% {" ~# l7 g7 [2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL# }) V+ j4 W- X* z- _6 U
2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window% k9 X: e6 u, ?8 o$ D7 P9 r
2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update9 _1 B7 C1 a4 k! h0 R! {, I& q8 X
2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'7 D. f8 K2 E& C$ N K/ A
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
8 Q* i9 K9 D: {0 {, C- T( ~2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present. ~6 ?$ O. h! T0 S, }' t: K, g
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes/ E- B9 w" f9 ~$ p
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
i" D! x, {9 H$ I2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.2 f) X* ?8 g: w" d2 W+ z$ L& f! y% l
2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash2 G1 a' S' `; i# S6 _) U) [: \* D
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.
. _, S% s! \9 e1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
, D: u3 O: L$ o- I" R1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)& r% D- K7 r; V4 R& X- o% G Q
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
( B1 Y& r4 Y' o0 H( q7 T2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
9 h# s$ o- {( i* F% D5 y' Q' [2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas. s2 {( I% L$ b
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice% \3 \0 ^4 L- P! Y+ d8 n' d9 g; i
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
1 q8 n( i2 H* ^/ m2 O2 x2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden7 k0 M e9 m7 U: }
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.61 Z/ g q/ \. \1 e1 o' u) v
2050674 APD PARTITION Cannot remove C-Point from a partitioned design0 p7 w6 g) @9 e! ]; _* }
2068814 APD WIREBOND Bond wires cross on auto-separate7 `6 n! I8 s/ q! `! Q
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open
# X- {' T* c1 ?& z6 d2 d# a5 D1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering4 w! P w" y2 } S7 w
2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
( C$ T) i# Z8 j2 r4 [1 t2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
) Z! \% M; g; y- s& F2 n* p2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
- c: I, U) q/ v4 ]2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
, n. r# q; C6 v9 ~6 Q2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
- O' g {- d1 r# \0 \& u2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
/ S# M1 D. G+ U2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM0 e/ d) o# Y# i( `% u& {" L/ p
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties
3 z7 u, O% T( d1 b2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
' `0 P1 V5 I/ E H2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses0 g7 b- I2 u/ e- \& S
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor& W1 I t# o/ \! I+ U8 S
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.) Q2 z# C8 W1 D+ r; }/ o/ W, l
2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
! d. Z4 g" x. E2 h9 w g2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked./ A, P1 E- T0 E+ ~# z8 Y
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character, Z/ D' P- _9 ]9 o
2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped4 s N! @. J b! b
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties& j8 T' \1 @9 b" G5 {; w* L
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
5 t4 x @- V& H$ ]* g2 P$ K2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
" E) v0 |& D3 _( Y) b2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
0 x# p y( K @0 K7 G2038021 PSPICE FRONTENDPLUGI Bias display is not updated% B9 ^ A! H: \7 ~ m$ r6 I# J
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
1 Z8 U; _. ~( {2 h6 I% C2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
1 y) Y- F1 ?( d# b* ]' z, u8 Z2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks7 K4 x" i [2 Z( C6 d k
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
' a$ x1 H5 h5 R$ l2 q+ \& i2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign7 y$ v. G& G9 f. p3 Y
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed2 X/ O% |7 d4 i. U0 k
2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'. T, x: s# [3 ^6 I6 a5 ~
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
4 I8 X) u' T" L" @% j: Q9 O2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
2 }; N X: m! Y3 L# y, H1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error
: H! e; n3 q; W, I6 L' _- Z1 ]2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files: |8 P$ x% I$ L
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed. c+ M# d- x8 G- X$ U# `6 p* p" S2 ?% K
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
& H7 L8 e8 U* Z8 a. w! {& d% q. t' [/ e1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name: U2 C+ |: M v$ f- e0 B8 [2 `0 q7 Z" S
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
2 G/ H* b9 n* i8 E- w1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping# p# ^9 r" O9 [ I
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor4 o9 \& R# O2 {1 w
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
, B% \# I: |, e! \0 d- J1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
3 x/ h' ]2 M6 L; h6 w1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM& Q3 A& C* F" t9 d
1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range) [3 E! t' M' o0 G4 P) Y- L3 t& }
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted., | w# d6 R* k4 z; L
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
. t( f% I. }1 A% Q" X: f1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
6 ?! S" _. u' _$ {& L+ c1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
0 x" n X8 P1 g5 e- I3 Z4 H& o1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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发表于 2019-5-3 15:45
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