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Hotfix_SPB17.20.054_wint_1of1.exe

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发表于 2019-5-3 15:45 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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本帖最后由 yangquan3 于 2019-5-4 15:13 编辑
/ A# w% Z$ n+ q' R! ?/ _( I6 k) g" \4 [5 k* M) h6 W( w2 P# c$ k
Hotfix_SPB17.20.054_wint_1of1.exe# X3 g9 y3 c! r, I9 E: j, g/ A+ \
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链接: https://pan.baidu.com/s/1r_llgvrGH_bebfSWaR7_5A 提取码: jpbn 复制这段内容后打开百度网盘手机App,操作更方便哦1 S$ e% I, U0 r  \' a

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发表于 2019-5-4 05:29 | 只看该作者
Fixed CCRs: SPB 17.2 HF054( a# H- Y4 H' f9 c5 g
04-26-2019
9 t! v$ P! T* I9 G, N========================================================================================================================================================7 X9 {* o! V4 r( F! ]
CCRID   Product            ProductLevel2 Title
+ }" g" H* @" r! O/ S8 r) ?========================================================================================================================================================; D% v! ?5 R& b
2060269 ADW                DBEDITOR      Unable to create ECAD type mixed-case schematic model attributes
) I# x2 V8 ]4 C% `/ @( J2030086 ADW                LRM           Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
& u" G; w1 o" X. d1975317 ADW                PART_BROWSER  Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
* h/ V' {2 q0 O6 @" g2076340 ADW                PART_BROWSER  .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache- v' i. w+ R$ S% n0 d/ F! _
2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
0 H8 O* N' t% `* E, c7 B1 Z( c' i  e2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design9 M5 f6 E; U3 Q) c
2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
8 e9 u3 q$ E) a* E) r2 v2054243 ALLEGRO_EDITOR     3D_CANVAS     Plating is not shown on stacked vias in 3D canvas& `& Z2 R* C6 s5 H- J% |% T8 J, R( m
2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation0 h. ?6 E% T' x7 n; O
2044980 ALLEGRO_EDITOR     ARTWORK       'Import - Artwork': PCB Editor stops responding and no artworks are loaded& ]8 R+ s8 r% Z3 U7 K% b* v) A
2060489 ALLEGRO_EDITOR     COLOR         SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off8 V! q) _- c) ^3 d5 @- d
2072695 ALLEGRO_EDITOR     COLOR         Clines of colored nets not colored when 'display_nohighlight_priority' is set4 l7 M* U; i/ [3 V1 n2 D7 g
2061203 ALLEGRO_EDITOR     CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
' d- t7 [: j3 o( v2010812 ALLEGRO_EDITOR     DATABASE      PCB Editor STEP model offsets should follow origin movements
/ b0 X* S2 \: f, ]  _9 j. _6 X# |2011993 ALLEGRO_EDITOR     DATABASE      Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin* o7 c# S( P0 p/ U; j4 R3 }/ q
2051596 ALLEGRO_EDITOR     DATABASE      Error for unsupported property in element' s0 W7 f* q# m  d: g6 Q
2056497 ALLEGRO_EDITOR     DATABASE      Place manual is slow4 d1 J; X4 e( l5 s
2059489 ALLEGRO_EDITOR     DATABASE      DBDOCTOR in batch mode with argument '-check_only' detects text error
$ l: ^; W1 r* X: _" ]2064268 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when running SKILL code
) B% @/ u; ?/ J" A2068588 ALLEGRO_EDITOR     DATABASE      Crash on opening release 16.6 design in 17.2-2016& @" A) w- H& t; l& V6 Y3 }; a
2079131 ALLEGRO_EDITOR     DATABASE      axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
5 M- w" C" e! |7 N$ o2034759 ALLEGRO_EDITOR     DFM           Importing DFT constraints on board does not assign csets to design but shows the csets$ I# p7 S( m, L6 c! j* I4 a; B; m
2039992 ALLEGRO_EDITOR     DFM           Cset is not set in Pastemask element of DFA when importing XML Constraint File.
, l! T. v7 ~5 r( _2046824 ALLEGRO_EDITOR     EXTRACT       Extracta ECL_NETWORK View reports incorrect pin layer.
. ~0 X& e/ _. X& j7 O2 N& J/ y2048912 ALLEGRO_EDITOR     IPC           Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'8 j7 E& b' d4 u4 G9 q& n
2066597 ALLEGRO_EDITOR     IPC           Graphical compare not completed because of self-intersecting shape locations
0 W9 E! [' o4 D- c; |" I. N( a2079719 ALLEGRO_EDITOR     IPC           IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
3 z0 S1 l! ]; k$ m2 T/ ]! p9 w2066229 ALLEGRO_EDITOR     NC            Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill' |9 j( k) ~+ V1 h
2070379 ALLEGRO_EDITOR     NC            After running backdrill some vias are shorted to other nets
5 ], d# [2 ?% A# k2041881 ALLEGRO_EDITOR     PAD_EDITOR    Difference in locations of drill in pad editor and symbol editor/ }: u, Q+ G, D7 c  p" u7 N
2058852 ALLEGRO_EDITOR     PAD_EDITOR    Net associations lost on refreshing vias
* w$ Z3 G; W% b: ]2061580 ALLEGRO_EDITOR     PAD_EDITOR    Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
! a. P3 T6 S& e1 o, L: I: I( I2048116 ALLEGRO_EDITOR     REPORTS       Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
7 w9 F# J! s# \7 H2038949 ALLEGRO_EDITOR     SCHEM_FTB     Netrev is slow if there is an input board file with many modified components2 Y- f/ B0 V) i: Q6 ], Z# `& @, V
2052758 ALLEGRO_EDITOR     SCHEM_FTB     Connectivity objects are being reported as Added and Deleted in Constraint Differences Report/ l8 k4 l5 b) K; ?! Q4 _
2066099 ALLEGRO_EDITOR     SCHEM_FTB     Inconsistent net names on export physical after changing net names in DE-HDL
& b/ X: n' }* c8 ?5 P2043882 ALLEGRO_EDITOR     SHAPE         Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window. {: P1 W& w  \9 ^5 s6 K+ o' V& D
2048483 ALLEGRO_EDITOR     SHAPE         Shapes not getting updated post backdrill update9 F4 g1 c9 h/ O: p; p
2052063 ALLEGRO_EDITOR     SHAPE         Cannot import IPC2581 due to 'Shape intersects with itself'1 K) |. G: T" r& J: ^
2056478 ALLEGRO_EDITOR     SHAPE         Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
1 v9 n9 h( z! h6 s0 y# y2058017 ALLEGRO_EDITOR     SHAPE         Shape not voiding correctly when fillets are present
6 _2 J9 U( T6 n+ \6 g2066473 ALLEGRO_EDITOR     SHAPE         Teardrops create strange copper shapes
) h; V6 O# W4 N0 r( p* ]) P, `1 P2079698 ALLEGRO_EDITOR     SHAPE         IPC2581 import fails with error 'Shapes intersects with itself'
0 o6 j2 |) M, z  F: T  h, j1 D2010569 ALLEGRO_EDITOR     SKILL         Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
* Y/ R: i" m) @- m- |% Q  [0 F2 }4 H2055055 ALLEGRO_EDITOR     SKILL         Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
. ~7 w2 ?* x4 Y) W* u. e6 ~2023755 ALLEGRO_EDITOR     STEP          Export STEP includes enclosure even when it is not selected.7 L1 x1 b  n' z2 o* k% E
1881233 ALLEGRO_EDITOR     UI_GENERAL    Green/white canvas without grid when creating a board file (File - New)
6 w; a+ C/ Q* f/ C- U& a9 ]6 L1900525 ALLEGRO_EDITOR     UI_GENERAL    Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
; u3 _% O1 @; _7 ~( s# h2003861 ALLEGRO_EDITOR     UI_GENERAL    Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048' g9 B/ \$ n' v! t# h+ G
2033958 ALLEGRO_EDITOR     UI_GENERAL    Incorrect canvas display on creating a design from the Start page and then opening an existing design
1 N( k& {" k* K6 N' z" \& f2053496 ALLEGRO_EDITOR     UI_GENERAL    Confirmation dialog is behind canvas0 V# ]2 u6 ?% o9 s
2054429 ALLEGRO_EDITOR     UI_GENERAL    Editor stops responding until choosing Done after clicking Zoom by Point twice/ U1 g$ R8 O1 [
2059707 ALLEGRO_EDITOR     UI_GENERAL    'HTTPS' links are not shown as hyperlinks when using allegro_html8 T& Q7 `* q" J3 z. s# ]7 h0 x
2063423 ALLEGRO_EDITOR     UI_GENERAL    Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden& n8 ^% G% k9 p0 G1 d5 t; d
2038105 APD                DRC_CONSTRAIN APD crashes on update DRC in release 16.6
5 T$ N  e1 P8 S0 S# s, i2 K2050674 APD                PARTITION     Cannot remove C-Point from a partitioned design  D$ n& |! S: o. j3 v8 c' O+ t9 Z
2068814 APD                WIREBOND      Bond wires cross on auto-separate
$ a) C. b+ e& o0 \0 K! {1967433 CAPTURE            OTHER         Cannot open DSN or OPJ files by double-clicking if Capture is already open
8 U8 U/ @7 U5 u# x: i1967332 CONCEPT_HDL        COMP_BROWSER  Crash in customer environment on clicking on last row border in PIM after filtering
# N) A( @; e9 S& w2001759 CONCEPT_HDL        COMP_BROWSER  Using Modify Component crashes Design Entry HDL- e" q0 u1 c" i: u
2020788 CONCEPT_HDL        COMP_BROWSER  Intermittent crash when clicking bottom edge of part selection table in the Modify Component window4 E9 }" F/ {$ {. O' @& }& p3 q7 [
2053578 CONCEPT_HDL        CONSTRAINT_MG Values specified for custom properties are not preserved
: L9 ?7 |4 j7 v# u2013002 CONCEPT_HDL        CORE          Ability to regenerate Netgroup names to remove '_1' suffix
/ I" `9 d+ {0 A: @: r" o2026637 CONCEPT_HDL        CORE          DE-HDL crashing often when launched from EDM Flow Manager; z( Y* _3 T3 `
2041145 CONCEPT_HDL        CORE          Set font size & color of netgroup names and netgroup taps0 b. ^: v4 Z8 O# {* z3 N3 ^% t# d
2056743 CONCEPT_HDL        CORE          NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
6 a4 Q7 X6 {$ \# i4 c; p% y: P; w6 b. V2065889 CONCEPT_HDL        CORE          DE-HDL Modify command moves location of attached symbol properties( y. o4 o/ O5 J4 a) {; K. h
2074410 CONCEPT_HDL        CORE          Full net connectivity not shown in Allegro PCB Editor.) o: Z" l0 q+ ]& m
2045717 CONCEPT_HDL        RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses7 P+ L! K. O/ t4 i
2045274 CONSTRAINT_MGR     CONCEPT_HDL   Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
( v! o0 {- o- v$ S5 R/ w. Z2050521 CONSTRAINT_MGR     OTHER         Unexpected Xnet removal from schematic when Export to PCB Layout is executed.$ n8 n$ U. W/ P+ |& W9 A9 t
2066270 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to edit note text containing comma3 y* p; g" M# I
2069181 PCB_LIBRARIAN      SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked./ q* P1 ]3 u2 c* m* L8 ~3 B1 H
2070007 PCB_LIBRARIAN      SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character# H4 i3 y/ _$ o  U6 X( P
2072793 PCB_LIBRARIAN      SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped2 T, f1 g, ?+ z8 M8 }- h5 j
2073138 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties1 x! M7 \( {; f( i6 H8 [9 F& w
1957458 PSPICE             FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated$ s7 T! Y. j+ X" S, U9 E6 M" G
2022211 PSPICE             FRONTENDPLUGI Bias Point results are not updated! l* f- k# b1 Y( f1 ~$ H, ]' G3 o
2031058 PSPICE             FRONTENDPLUGI PSpice bias values are not getting updated
. T% v8 z: H, ], }5 g3 M2038021 PSPICE             FRONTENDPLUGI Bias display is not updated: W) x$ A0 I5 b2 }; M; V' S9 f
2055274 PSPICE             FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open3 g6 A' j( ?1 k( v$ h
2053432 RF_PCB             OTHER         Property on RF component not transferred to new design not containing the component
* E8 g+ Y, I  T& N% |% [0 u2003341 SCM                SCHGEN        Unable to generate a schematic for hierarchical blocks
" W6 F! g/ Z& i2069924 SIP_LAYOUT         DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.3 ^2 X$ k& B7 ]9 ^
2067894 SIP_LAYOUT         OTHER         sip database size is enormous for a small component definition used in fdesign9 q% m9 y( j5 ]: i9 k' @
2067987 SIP_LAYOUT         OTHER         Orphaned die attachment in SiP Layout cannot be removed/ e- ~8 ~% e8 d8 N
2072857 SIP_LAYOUT         OTHER         SiP Layout crashes when using Find by Query and choosing 'Symbols'
% S8 F8 ]! X1 `8 Z2068973 SIP_LAYOUT         REPORTS       SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
9 @( z: E  x0 g, j# h2059533 SIP_LAYOUT         SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
( I, H3 v8 d! J$ W3 @# M: c1981749 SYSTEM_CAPTURE     ARCHIVER      System Capture: Archiving a design from the Tcl command window results in error3 z4 H2 g3 I, T; M$ x
2054869 SYSTEM_CAPTURE     AUTOMATION    syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files4 Q8 v2 t4 v4 n7 y! {
1966488 SYSTEM_CAPTURE     CANVAS_EDIT   New folder rename box does not show the text typed.
7 ?, B+ H! h: p- `7 @* _' p: E1814813 SYSTEM_CAPTURE     COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
  y0 E/ R  \$ x! r1977673 SYSTEM_CAPTURE     COMPONENT_BRO adding reference blocks through add component error when cell name matches design name' W: L. V4 Y: Q5 L* f- w. U3 a: `
2027100 SYSTEM_CAPTURE     COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
4 k, M. _, _0 {2 {: p# {' E) s1961274 SYSTEM_CAPTURE     CONNECTIVITY_ Xnet removed during pin swapping
  {3 Z- }7 `: k7 c/ T& J& t  P8 n8 `1 Q2041879 SYSTEM_CAPTURE     CONNECTIVITY_ xnets on net with only pull-up resistor) R( }% P; i. u* R. M( D7 @
1889238 SYSTEM_CAPTURE     COPY_PASTE    Wire fails to connect during copy and paste
! r) G% q7 W* B* V1993146 SYSTEM_CAPTURE     DESIGN_EXPLOR Cannot move page up by only one position
( L& c4 K! ?. N1910941 SYSTEM_CAPTURE     MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM  b, V- o6 k: |' ~
1902347 SYSTEM_CAPTURE     PRINT         Prints all sheets if one sheet is specified as the print range% E1 q  G$ ~: B8 S* p
2041272 SYSTEM_CAPTURE     SMART_PDF     Smart pdf displays component outline when component is not de-highlighted., D3 n6 I/ y& \! C1 F. w
2065768 SYSTEM_CAPTURE     SMART_PDF     Custom Variable in Table Object not getting passed to PDF
4 D1 I  c" @7 Z( W1969243 SYSTEM_CAPTURE     VARIANT_MANAG Export variant does not name file correctly if the filename contains a space5 E7 y: W: s) U6 s: p1 Y4 n
1990258 SYSTEM_CAPTURE     VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number/ \- d$ f5 {" g$ K
1992250 SYSTEM_CAPTURE     WORKSPACE     Double-clicking a .CPM file runs System Capture but does not open project

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发表于 2019-5-4 05:27 | 只看该作者
本帖最后由 linguohua 于 2019-5-4 05:29 编辑 , I, b1 C5 C" K% h( G' N
金志峰 发表于 2019-5-4 01:01; r; }, R. _1 i; q& r
麻烦先发个ccr看看吧
抱歉,本来想复制到回帖里面,发现格式全乱了。因此直接看下面连接比较好:
9 d+ w% w. x1 ]+ X8 k- Q( J* {; n, Ohttps://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=138247&page=5

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发表于 2019-5-4 05:27 | 只看该作者
金志峰 发表于 2019-5-4 01:01) z7 G# Z/ W5 n5 [
麻烦先发个ccr看看吧
  N- i2 x: q+ E+ p8 a
https://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=138247&page=5+ p% B7 S, e0 `9 y2 \" n
  • TA的每日心情
    开心
    2025-6-14 15:01
  • 签到天数: 983 天

    [LV.10]以坛为家III

    2#
    发表于 2019-5-3 16:18 | 只看该作者
    更新得真快啊!
  • TA的每日心情
    郁闷
    2025-6-15 15:52
  • 签到天数: 26 天

    [LV.4]偶尔看看III

    3#
    发表于 2019-5-3 16:37 | 只看该作者
    更新頻率真是令人嘆為觀止。。。
  • TA的每日心情
    开心
    2019-11-20 15:15
  • 签到天数: 1 天

    [LV.1]初来乍到

    6#
    发表于 2019-5-3 22:06 | 只看该作者
    给个网盘链接把 威望太贵了

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    8#
    发表于 2019-5-4 01:00 | 只看该作者
    楼主貌似下了几天了。。。

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    9#
    发表于 2019-5-4 01:01 | 只看该作者
    麻烦先发个ccr看看吧

    点评

    https://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=138247&page=5  详情 回复 发表于 2019-5-4 05:27
    Fixed CCRs: SPB 17.2 HF05404-26-2019========================================================================================================================================================CCRID Prod  详情 回复 发表于 2019-5-4 05:27
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