Hotfix_SPB17.20.054_wint_1of1.exe

yangquan3

Hotfix_SPB17.20.054_wint_1of1.exe
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; l4 o5 m5 G: H' G链接: https://pan.baidu.com/s/1r_llgvrGH_bebfSWaR7_5A 提取码: jpbn 复制这段内容后打开百度网盘手机App，操作更方便哦
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linguohua

Fixed CCRs: SPB 17.2 HF054
. r! `: ]0 A8 J5 {8 o* K04-26-2019
- D  Y4 m" S, @) e7 O9 N========================================================================================================================================================
9 L5 X0 U: y( _6 `. W6 @CCRID   Product            ProductLevel2 Title
========================================================================================================================================================
% C4 z+ f( |/ h4 A2060269 ADW                DBEDITOR      Unable to create ECAD type mixed-case schematic model attributes
2030086 ADW                LRM           Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property
1 n0 J" s0 J; E- }7 D7 L1975317 ADW                PART_BROWSER  Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
2076340 ADW                PART_BROWSER  .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
+ f; K) _) y- h) p- S# J2025147 ADW                TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
2025201 ADW                TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
2056694 ADW                TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
2054243 ALLEGRO_EDITOR     3D_CANVAS     Plating is not shown on stacked vias in 3D canvas
2054327 ALLEGRO_EDITOR     3D_CANVAS     3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation
: Z9 d" b+ E0 p# C2044980 ALLEGRO_EDITOR     ARTWORK       'Import - Artwork': PCB Editor stops responding and no artworks are loaded
" X4 x* ?/ o8 t" c( K! g) z2060489 ALLEGRO_EDITOR     COLOR         SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
2072695 ALLEGRO_EDITOR     COLOR         Clines of colored nets not colored when 'display_nohighlight_priority' is set
0 ^9 P6 u7 m) t- e+ J" A. R6 z2061203 ALLEGRO_EDITOR     CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
2010812 ALLEGRO_EDITOR     DATABASE      PCB Editor STEP model offsets should follow origin movements
! Z# ?( `4 ]) y0 Q8 c) Q; {2011993 ALLEGRO_EDITOR     DATABASE      Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin
2051596 ALLEGRO_EDITOR     DATABASE      Error for unsupported property in element
2056497 ALLEGRO_EDITOR     DATABASE      Place manual is slow
3 N: W4 o2 ?4 j# ^$ x; e2059489 ALLEGRO_EDITOR     DATABASE      DBDOCTOR in batch mode with argument '-check_only' detects text error
- M8 c: y6 F! w1 X; Y2064268 ALLEGRO_EDITOR     DATABASE      PCB Editor crashes when running SKILL code
2068588 ALLEGRO_EDITOR     DATABASE      Crash on opening release 16.6 design in 17.2-2016
, h" w, {* w! O8 y. k2079131 ALLEGRO_EDITOR     DATABASE      axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
% z" K2 n" v' }9 Z2034759 ALLEGRO_EDITOR     DFM           Importing DFT constraints on board does not assign csets to design but shows the csets
( P- J& f9 @6 z8 H8 u# j2039992 ALLEGRO_EDITOR     DFM           Cset is not set in Pastemask element of DFA when importing XML Constraint File.
2046824 ALLEGRO_EDITOR     EXTRACT       Extracta ECL_NETWORK View reports incorrect pin layer.
2048912 ALLEGRO_EDITOR     IPC           Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
3 X% r) y, [6 j2066597 ALLEGRO_EDITOR     IPC           Graphical compare not completed because of self-intersecting shape locations
! {5 a9 w- ~( a! [4 _2079719 ALLEGRO_EDITOR     IPC           IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
& ^! d7 l5 G% Y- Z, c: N: Z) Q2066229 ALLEGRO_EDITOR     NC            Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill
4 s9 p% j$ b: Q; _9 a4 Y0 y7 n& I2070379 ALLEGRO_EDITOR     NC            After running backdrill some vias are shorted to other nets
2041881 ALLEGRO_EDITOR     PAD_EDITOR    Difference in locations of drill in pad editor and symbol editor
" h+ {: L' f  [2058852 ALLEGRO_EDITOR     PAD_EDITOR    Net associations lost on refreshing vias
2061580 ALLEGRO_EDITOR     PAD_EDITOR    Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
0 r- |- v/ V2 V% Q% c2048116 ALLEGRO_EDITOR     REPORTS       Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
+ \0 v* O6 y; t0 ?- x$ w5 j2038949 ALLEGRO_EDITOR     SCHEM_FTB     Netrev is slow if there is an input board file with many modified components
2052758 ALLEGRO_EDITOR     SCHEM_FTB     Connectivity objects are being reported as Added and Deleted in Constraint Differences Report
, M! }2 @4 i( F3 t# z& i2066099 ALLEGRO_EDITOR     SCHEM_FTB     Inconsistent net names on export physical after changing net names in DE-HDL
2043882 ALLEGRO_EDITOR     SHAPE         Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
2 E! r0 o3 @" Q. [$ ^5 Y2048483 ALLEGRO_EDITOR     SHAPE         Shapes not getting updated post backdrill update
2052063 ALLEGRO_EDITOR     SHAPE         Cannot import IPC2581 due to 'Shape intersects with itself'
2056478 ALLEGRO_EDITOR     SHAPE         Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
2058017 ALLEGRO_EDITOR     SHAPE         Shape not voiding correctly when fillets are present
2066473 ALLEGRO_EDITOR     SHAPE         Teardrops create strange copper shapes
2079698 ALLEGRO_EDITOR     SHAPE         IPC2581 import fails with error 'Shapes intersects with itself'
2010569 ALLEGRO_EDITOR     SKILL         Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
2055055 ALLEGRO_EDITOR     SKILL         Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
2023755 ALLEGRO_EDITOR     STEP          Export STEP includes enclosure even when it is not selected.
8 h0 `2 S- j, l; Q: e1881233 ALLEGRO_EDITOR     UI_GENERAL    Green/white canvas without grid when creating a board file (File - New)
3 O, {: T% ?% C- {3 `* @! ?9 G1900525 ALLEGRO_EDITOR     UI_GENERAL    Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
2003861 ALLEGRO_EDITOR     UI_GENERAL    Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
8 E% Q8 m* r; J- _7 [2033958 ALLEGRO_EDITOR     UI_GENERAL    Incorrect canvas display on creating a design from the Start page and then opening an existing design
2053496 ALLEGRO_EDITOR     UI_GENERAL    Confirmation dialog is behind canvas
0 l) T' I; S, Y7 p, p; w/ k2054429 ALLEGRO_EDITOR     UI_GENERAL    Editor stops responding until choosing Done after clicking Zoom by Point twice
2059707 ALLEGRO_EDITOR     UI_GENERAL    'HTTPS' links are not shown as hyperlinks when using allegro_html
# e3 i% ^" Y( |3 j6 H* \# O8 j2063423 ALLEGRO_EDITOR     UI_GENERAL    Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
2038105 APD                DRC_CONSTRAIN APD crashes on update DRC in release 16.6
2050674 APD                PARTITION     Cannot remove C-Point from a partitioned design
: q: _9 [; O$ L& [" _5 d2068814 APD                WIREBOND      Bond wires cross on auto-separate
1967433 CAPTURE            OTHER         Cannot open DSN or OPJ files by double-clicking if Capture is already open
1967332 CONCEPT_HDL        COMP_BROWSER  Crash in customer environment on clicking on last row border in PIM after filtering
2001759 CONCEPT_HDL        COMP_BROWSER  Using Modify Component crashes Design Entry HDL
2020788 CONCEPT_HDL        COMP_BROWSER  Intermittent crash when clicking bottom edge of part selection table in the Modify Component window
2053578 CONCEPT_HDL        CONSTRAINT_MG Values specified for custom properties are not preserved
2013002 CONCEPT_HDL        CORE          Ability to regenerate Netgroup names to remove '_1' suffix
2026637 CONCEPT_HDL        CORE          DE-HDL crashing often when launched from EDM Flow Manager
2041145 CONCEPT_HDL        CORE          Set font size & color of netgroup names and netgroup taps
2056743 CONCEPT_HDL        CORE          NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
2065889 CONCEPT_HDL        CORE          DE-HDL Modify command moves location of attached symbol properties
6 R) [/ `( B' }) S3 I7 @8 Q9 @4 A2074410 CONCEPT_HDL        CORE          Full net connectivity not shown in Allegro PCB Editor.
2045717 CONCEPT_HDL        RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
2045274 CONSTRAINT_MGR     CONCEPT_HDL   Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
2050521 CONSTRAINT_MGR     OTHER         Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
  U. s' m- A4 T7 z7 Z* M2066270 PCB_LIBRARIAN      SYMBOL_EDITOR Unable to edit note text containing comma
; w: \, g0 ~. R, P% n' W1 n' ?9 y2069181 PCB_LIBRARIAN      SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
2070007 PCB_LIBRARIAN      SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
2072793 PCB_LIBRARIAN      SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped
2073138 PCB_LIBRARIAN      SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
1957458 PSPICE             FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
2022211 PSPICE             FRONTENDPLUGI Bias Point results are not updated
' S! A; i6 {/ S8 o$ e2031058 PSPICE             FRONTENDPLUGI PSpice bias values are not getting updated
2038021 PSPICE             FRONTENDPLUGI Bias display is not updated
! F- j! I# ]4 I6 v+ ?/ G. F2055274 PSPICE             FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open
4 }5 H. t' e2 y! I: y. }2053432 RF_PCB             OTHER         Property on RF component not transferred to new design not containing the component
2003341 SCM                SCHGEN        Unable to generate a schematic for hierarchical blocks
2069924 SIP_LAYOUT         DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.
2067894 SIP_LAYOUT         OTHER         sip database size is enormous for a small component definition used in fdesign
2067987 SIP_LAYOUT         OTHER         Orphaned die attachment in SiP Layout cannot be removed
2072857 SIP_LAYOUT         OTHER         SiP Layout crashes when using Find by Query and choosing 'Symbols'
2068973 SIP_LAYOUT         REPORTS       SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
( m# I, N+ V& Q2 m1 ?' e' q; N+ [2059533 SIP_LAYOUT         SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
/ V" |- J. r: t1 I" L1981749 SYSTEM_CAPTURE     ARCHIVER      System Capture: Archiving a design from the Tcl command window results in error
4 V- E' y7 t) `3 ]( j6 ]! @6 q2054869 SYSTEM_CAPTURE     AUTOMATION    syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
1966488 SYSTEM_CAPTURE     CANVAS_EDIT   New folder rename box does not show the text typed.
1814813 SYSTEM_CAPTURE     COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
1977673 SYSTEM_CAPTURE     COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
2027100 SYSTEM_CAPTURE     COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
6 n& v- i. \( r* }; d2 d; {1961274 SYSTEM_CAPTURE     CONNECTIVITY_ Xnet removed during pin swapping
  ^0 a, u. W9 i% s' V2041879 SYSTEM_CAPTURE     CONNECTIVITY_ xnets on net with only pull-up resistor
1889238 SYSTEM_CAPTURE     COPY_PASTE    Wire fails to connect during copy and paste
. `1 b+ w; L7 P6 T( J1993146 SYSTEM_CAPTURE     DESIGN_EXPLOR Cannot move page up by only one position
1910941 SYSTEM_CAPTURE     MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
1902347 SYSTEM_CAPTURE     PRINT         Prints all sheets if one sheet is specified as the print range
2041272 SYSTEM_CAPTURE     SMART_PDF     Smart pdf displays component outline when component is not de-highlighted.
2065768 SYSTEM_CAPTURE     SMART_PDF     Custom Variable in Table Object not getting passed to PDF
  x8 G: f. |7 F( S1969243 SYSTEM_CAPTURE     VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
1990258 SYSTEM_CAPTURE     VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
1992250 SYSTEM_CAPTURE     WORKSPACE     Double-clicking a .CPM file runs System Capture but does not open project

linguohua

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金志峰 发表于 2019-5-4 01:01
1 A  e! K  i7 O0 d/ K9 M/ f& a5 b麻烦先发个ccr看看吧

抱歉，本来想复制到回帖里面，发现格式全乱了。因此直接看下面连接比较好：
https://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=138247&page=5

linguohua

金志峰 发表于 2019-5-4 01:01
! y/ w1 ]' B+ L/ {. f麻烦先发个ccr看看吧

7 X4 |1 P0 [  v3 Rhttps://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=138247&page=5
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th2010-gc01

更新得真快啊！

ethernet

更新頻率真是令人嘆為觀止。。。

llntech

good

llntech

good

逸步舞秋风

给个网盘链接把 威望太贵了

kewin_wang

感谢楼主！

金志峰

楼主貌似下了几天了。。。

金志峰

麻烦先发个ccr看看吧

Geant168

great

vasylll

thank

Deny

thanks