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Fixed CCRs: SPB 17.2 HF054
8 Q3 r8 q8 v6 S8 @% T04-26-2019
1 m1 g# X2 I0 x/ `; M& s========================================================================================================================================================
9 D( C& q8 i$ WCCRID Product ProductLevel2 Title
0 x$ y S/ V$ B8 M5 T8 p========================================================================================================================================================
6 _$ }9 l, z6 @" m2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
) q( Z: a4 ^- e `; C& b3 O' P- C2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property/ s' g2 v. h1 [
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser( A8 t- h* T8 j3 @/ F U. h
2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache
4 p6 N$ N: [9 h: H) [2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name
}+ L5 }: l$ o" ?2 P, H2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
2 N% }/ u! |% T( N7 e' U( R2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
/ D2 {) {: H& f2 _! K2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas
" k7 l5 R& n# r0 E+ c5 X( b2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation5 d- M3 M8 z( w# B
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded4 c" \# F; l0 k& _ R
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
2 z5 Z! t {2 ^6 o1 e) S- p2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set
5 ?# l/ P( j/ D; ], a/ m2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone
) Y3 b5 }* U2 c+ L4 P8 R7 v2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements7 P B5 p# X+ B" d/ B; }
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin# G+ M6 z% G9 U, d. r
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element5 J+ U' _6 i. _* n; @
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow. J4 r# a2 y% q+ r
2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error
' X) b, U; A( O2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
- F* f7 C% Z1 D- p1 i2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
6 U& P* e" @- @( f2 Z* s+ O2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error$ _6 N4 D. K9 r% a& ]
2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets
8 m5 e1 i! z. p- r2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.% I- z' Y2 E) i. ~, ]& M0 Q1 s/ a! @
2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer./ h: T1 E3 V( {1 F
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
6 u5 @! k# h3 g1 k9 w. D! Q \5 _2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations9 @; k& W" m9 a2 j' B* @0 U! K
2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
6 a1 N+ s* p5 |. C2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill, B, V. o1 p5 A3 r S
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets( S, Y" P; W5 R! X" r( X. p/ `, H
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor) p4 p& z# t& ^
2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias+ @) s+ Y' k! B3 h7 {, F6 S; i
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor' t. t# V- I. b3 J
2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
7 H# p. n2 B/ A+ t* k/ N3 V2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components' k+ j% U8 Z; w! T# v- P
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report2 w" W+ n' z4 k7 W- n/ \
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
# Z' J: {& n, P6 l2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
0 {; ?9 K( G$ b1 n( G2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
5 ?0 t* [5 U3 o' b0 Z2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself' U" W# K/ D% b/ _' C" X1 Y
2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape/ p" }7 K4 e4 _8 ^
2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present
7 _" K# l0 m# p. L0 a2 M2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes/ _2 U) X, C) n! G! z) k
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
! b; J) R; I& H2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
1 L0 f5 W' \" S2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash
( ` Y8 T" l/ A3 Y4 c0 N: R' p2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.( ]2 ~' d1 _8 T8 j
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)7 X5 m- @. {7 a
1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)
6 L: T# _( M3 ^/ \/ Q g2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
6 ^" `% [; W& N( q' b6 i2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
0 i/ O2 m/ `) R) W1 v) x2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas% ?0 @% m3 W+ @% z
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice: e( P5 [# D) W, { u4 `3 R
2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
) H( o. W3 B# H; H- J2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden
; \# I9 v' I% o( d* m2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.65 a' D/ ?* i- W3 H/ ^/ Q
2050674 APD PARTITION Cannot remove C-Point from a partitioned design0 ~# R- o" e; Z" J3 _! x
2068814 APD WIREBOND Bond wires cross on auto-separate0 ~- o Z' Z# W- J
1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open6 n. p7 ~/ g6 q( R! ^- ^- N) g
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering0 X2 O/ [" J3 ~ X
2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL
8 N/ I7 J9 T( _8 ^7 k2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window; W' Z0 f0 P V. h
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
5 @- D" q6 ~1 {' V4 d2 o0 N2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
) t' A. P" z; |0 Q# R( H2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
- F- z# t4 w' Y7 W* v7 o2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
/ F- @5 g' D& l1 {+ |2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM5 b7 z0 F: b9 n: s2 U6 `7 ~$ r0 L
2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties3 I2 Q& U4 q3 Z" I- z2 e1 o6 M
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
0 Y$ @. S, h: n& z$ I2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses" h# q9 t( {% g- O' H2 ~
2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor
% E: }( I# C; t+ l+ v$ v, `' i4 b3 V2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
+ s+ g4 ]5 m2 }7 ?. L2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
. Q* F" R8 J; c0 X2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.
2 b7 B/ y3 g8 [+ t2 G' k$ X2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
; ?" p& |8 z- m6 g9 m2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped! Z6 }/ ?/ C" V* X
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties
2 @2 D' s$ a: y1 L1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
7 G3 A6 {& d' t4 ?5 g2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
1 d2 `6 E) H& o) W2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated6 y. y4 ?* W7 s. o X: \& h0 |
2038021 PSPICE FRONTENDPLUGI Bias display is not updated. G0 |# H' F8 Y! K% m' u- t
2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open. Z9 S" Q$ O/ [
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component
/ D3 e5 n4 ~* P# ]2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks! ]/ K% W* `/ N2 r7 ~8 L k2 t& a% ^
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.+ q7 t0 l) Z$ w9 a4 g
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign
' T/ ^% `' f/ M, J% ]5 y2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
1 j/ N, c4 A$ G* |: k& d4 L2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'! O* `( h3 m- o; C t( H" V
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052
/ e$ V$ Z* Q# ~% q1 n2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
2 i, \# P- Z; V/ w2 k1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error/ Q" U6 g+ O; W4 }0 c/ ~
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files5 |7 T8 A$ z( S3 Q( `* I7 U/ g
1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.+ D9 ?3 V; L* M# p5 U! J0 h
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
0 X3 _% d! D; a E2 z" P1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name2 A0 a1 W& K1 s$ l$ B& F. }
2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written- `# P, A9 @% _& ]! [8 Y
1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping6 P( \; s, |% m; k5 U5 ^
2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor/ u/ ^1 `" d$ {6 t9 D$ f
1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste: `0 K9 X6 r8 k* m/ }
1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
- f3 L# p/ D1 G# J1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
v+ D& I5 c: ?+ }( D1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range
; Q6 U$ z: c* r, L2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.$ k9 i2 t9 Y j0 Z$ Y
2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF
1 a4 g& v2 W7 Q* h6 P9 I4 g1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
3 A3 i, V. B' v/ C! _" V5 ~1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number
$ O: w$ i2 e5 `, u3 ^, F; ^! h8 M1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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