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Fixed CCRs: SPB 17.2 HF054
4 H+ q1 p- {3 V6 k. ~04-26-2019 n; G- h, n" k6 D8 J L/ d
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3 v4 {/ {1 j# s# wCCRID Product ProductLevel2 Title$ }4 S h2 k& s* m% B, C
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0 t: @& E- L. I% h1 ^2060269 ADW DBEDITOR Unable to create ECAD type mixed-case schematic model attributes
! ]( O5 J& f/ b' W1 L1 A2030086 ADW LRM Cache part_table.ptf made by LRM Update cannot be read if it has null value in key property* G" }6 a, Q- t+ ]9 _4 T6 i
1975317 ADW PART_BROWSER Space at the end of line in CDS.LIB results in zero libraries being shown in new component browser
3 ?# C2 h" [5 C9 c8 d2076340 ADW PART_BROWSER .helix folder needs to be deleted for PTF changes to take effect and to convert a design to cache( n, }. b( d1 x* l$ X
2025147 ADW TDO-SHAREPOIN Design Management stops responding when a board file is deleted and then checked in with the same name5 m* d/ t9 I1 F# L) d% R, T/ ^$ f- c
2025201 ADW TDO-SHAREPOIN Getting error message (SPDWSD-20) when logging in to team design
6 R, S! e! e* g; `- i9 s% x2056694 ADW TDO-SHAREPOIN Design Management stops responding on checking in an object with the same name as a previously deleted object
9 K% ]/ Z* e7 c; K" O/ G2054243 ALLEGRO_EDITOR 3D_CANVAS Plating is not shown on stacked vias in 3D canvas" |" R" p, ^$ I8 W4 `. c
2054327 ALLEGRO_EDITOR 3D_CANVAS 3D Canvas error: All bend operations are disabled due to licensing and/or DLL installation2 I& W3 T/ \& {2 \
2044980 ALLEGRO_EDITOR ARTWORK 'Import - Artwork': PCB Editor stops responding and no artworks are loaded5 U6 L! d- h/ K' U" P5 X
2060489 ALLEGRO_EDITOR COLOR SKILL axlGlobalVisibility() issue in a partition file: VIA/SOLDERMASK_TOP subclass visibility not turned off
6 J4 p4 N, l( {. K# G$ B1 J1 ~9 L r2072695 ALLEGRO_EDITOR COLOR Clines of colored nets not colored when 'display_nohighlight_priority' is set) f) R" D$ f# `$ D2 C
2061203 ALLEGRO_EDITOR CROSS_SECTION Importing cross-section from single stackup to multiple stackup adding additional layers to the primary zone2 s' n/ l# Y/ W7 p) \3 d. p8 F
2010812 ALLEGRO_EDITOR DATABASE PCB Editor STEP model offsets should follow origin movements W$ l' `& c$ D9 z5 h, v n, G
2011993 ALLEGRO_EDITOR DATABASE Change STEP model mapping when Symbol Origin is changed in DRA using Setup > Change Drawing Origin% c/ l# [' A, K9 L$ H# N, }$ ~
2051596 ALLEGRO_EDITOR DATABASE Error for unsupported property in element/ R9 _" S! S4 M: q2 Z& I; u' B7 f
2056497 ALLEGRO_EDITOR DATABASE Place manual is slow
3 Z2 Y2 t/ E6 R) |6 E5 Q1 D2059489 ALLEGRO_EDITOR DATABASE DBDOCTOR in batch mode with argument '-check_only' detects text error4 j$ w6 M0 g5 Q5 O
2064268 ALLEGRO_EDITOR DATABASE PCB Editor crashes when running SKILL code
* H# F. Q6 [8 e/ D7 Z6 \3 n+ y B' ]2068588 ALLEGRO_EDITOR DATABASE Crash on opening release 16.6 design in 17.2-2016
$ j& [2 [) H' C5 E- o3 f2079131 ALLEGRO_EDITOR DATABASE axlChangeNet crashes PCB Editor in fast shape mode with Microsoft Visual C++ Runtime Library Error
, R; X2 T6 l# T2034759 ALLEGRO_EDITOR DFM Importing DFT constraints on board does not assign csets to design but shows the csets: {8 I* U$ R( p3 ?0 w5 j$ J' U
2039992 ALLEGRO_EDITOR DFM Cset is not set in Pastemask element of DFA when importing XML Constraint File.
, s1 e1 N Z5 v- D+ ?2046824 ALLEGRO_EDITOR EXTRACT Extracta ECL_NETWORK View reports incorrect pin layer.' [, `2 x2 M% y2 Z ~* R+ {
2048912 ALLEGRO_EDITOR IPC Running PCB Design Compare - Graphic mode reports ERROR (SPMHA1-273) 'Shape intersects with itself'
2 ^- Z; Q2 \7 y) y6 F a2066597 ALLEGRO_EDITOR IPC Graphical compare not completed because of self-intersecting shape locations
- @6 R' l5 \4 t. M& T2079719 ALLEGRO_EDITOR IPC IPC2581 import fails with error 'Failed to add (LW)POLYLINE'
4 [1 B+ o6 B' F9 Y/ K2066229 ALLEGRO_EDITOR NC Tool code missing in backdrill NC file on choosing 'Optimize Drill Head Travel' in NC Drill; V( g7 g5 k; \8 B) d* Q3 s# R7 ~
2070379 ALLEGRO_EDITOR NC After running backdrill some vias are shorted to other nets- A s( E7 C7 C0 o
2041881 ALLEGRO_EDITOR PAD_EDITOR Difference in locations of drill in pad editor and symbol editor
/ `" D( Y0 U3 M0 ~2058852 ALLEGRO_EDITOR PAD_EDITOR Net associations lost on refreshing vias; W3 \. ^/ }5 y S4 Q
2061580 ALLEGRO_EDITOR PAD_EDITOR Lock Layer Span settings specified in padstack editor not reflected in PCB Editor
- B# i1 k3 m3 z! K R2048116 ALLEGRO_EDITOR REPORTS Extracta command files not visible in Tools-->Reports when there is a space present in the textpath variable
' j0 ]3 \* ]' x8 A$ {0 T" }1 g: x2038949 ALLEGRO_EDITOR SCHEM_FTB Netrev is slow if there is an input board file with many modified components$ e% i( K8 \1 b: m& L
2052758 ALLEGRO_EDITOR SCHEM_FTB Connectivity objects are being reported as Added and Deleted in Constraint Differences Report+ R% g- d: B5 a4 z5 {
2066099 ALLEGRO_EDITOR SCHEM_FTB Inconsistent net names on export physical after changing net names in DE-HDL
( `" }' U* U% N1 ~2043882 ALLEGRO_EDITOR SHAPE Shapes not updated to 'Minimum aperture for gap width' in Global Dynamic Shape Parameters window
4 X+ x% }! r- _# a6 ~2048483 ALLEGRO_EDITOR SHAPE Shapes not getting updated post backdrill update
. ~! \3 ]/ U8 n8 a2052063 ALLEGRO_EDITOR SHAPE Cannot import IPC2581 due to 'Shape intersects with itself'
$ l# U- V; i8 H9 T& `2056478 ALLEGRO_EDITOR SHAPE Editing shape by sliding segment causes PCB Editor to fail due to 0-length segment in shape
, S. `# O& h2 f# G+ n2058017 ALLEGRO_EDITOR SHAPE Shape not voiding correctly when fillets are present6 b1 J. a9 J1 I- J5 h8 p9 ~* U! Z
2066473 ALLEGRO_EDITOR SHAPE Teardrops create strange copper shapes# C. r, v. U9 ~) t1 ~- g
2079698 ALLEGRO_EDITOR SHAPE IPC2581 import fails with error 'Shapes intersects with itself'
# Q# [) A+ t3 s& f2010569 ALLEGRO_EDITOR SKILL Using SKILL to add 'nil' to a DRC object following a 'println' statement crashes PCB Editor in HotFix 048.
; c# |* j, ?. g+ l6 G) x2055055 ALLEGRO_EDITOR SKILL Using SKILL to add a 'nil' property value to a String causes Allegro PCB Editor to crash% [+ ~' g% j$ j. i% {& q) X
2023755 ALLEGRO_EDITOR STEP Export STEP includes enclosure even when it is not selected.# G) _8 f/ r$ i! Q' F
1881233 ALLEGRO_EDITOR UI_GENERAL Green/white canvas without grid when creating a board file (File - New)
- T! Z+ G5 l0 \$ M! x1900525 ALLEGRO_EDITOR UI_GENERAL Resizing the update symbols UI causes the options to overlap and jumble up (refresh issue)# M. m9 k3 O3 n6 w F6 V8 A8 u
2003861 ALLEGRO_EDITOR UI_GENERAL Same y-coordinate returned for different vertical positions when creating board outline in HotFix 048
0 y" u+ ?6 N4 M3 u7 r2033958 ALLEGRO_EDITOR UI_GENERAL Incorrect canvas display on creating a design from the Start page and then opening an existing design
0 t) B9 n4 @% W/ Z O1 `2053496 ALLEGRO_EDITOR UI_GENERAL Confirmation dialog is behind canvas% }$ J8 D; K2 T; }+ q; k6 {7 @! i
2054429 ALLEGRO_EDITOR UI_GENERAL Editor stops responding until choosing Done after clicking Zoom by Point twice
$ v- x3 `! E" s9 A+ k( ]2059707 ALLEGRO_EDITOR UI_GENERAL 'HTTPS' links are not shown as hyperlinks when using allegro_html
' j0 m; q1 P# j4 X% [ i' \2063423 ALLEGRO_EDITOR UI_GENERAL Blocking dialog popped up by axlUIPrompt() goes behind the canvas and is hidden& q+ u+ Q) p# }5 D
2038105 APD DRC_CONSTRAIN APD crashes on update DRC in release 16.6- \+ `9 W; A. H- f
2050674 APD PARTITION Cannot remove C-Point from a partitioned design- G1 f( O' s+ @4 K$ P5 j3 y+ \
2068814 APD WIREBOND Bond wires cross on auto-separate
& b J( e% ^' b4 ~2 l% Y3 c. f1967433 CAPTURE OTHER Cannot open DSN or OPJ files by double-clicking if Capture is already open4 E: \$ o j% }% {
1967332 CONCEPT_HDL COMP_BROWSER Crash in customer environment on clicking on last row border in PIM after filtering
+ ` L, f$ \, ?* L- ~2001759 CONCEPT_HDL COMP_BROWSER Using Modify Component crashes Design Entry HDL0 Z& e! i4 y# q
2020788 CONCEPT_HDL COMP_BROWSER Intermittent crash when clicking bottom edge of part selection table in the Modify Component window0 x9 r, F: F& i1 F( f
2053578 CONCEPT_HDL CONSTRAINT_MG Values specified for custom properties are not preserved
. q5 l0 T' _! H4 Z2013002 CONCEPT_HDL CORE Ability to regenerate Netgroup names to remove '_1' suffix
) h9 l, W# m7 b V/ N2026637 CONCEPT_HDL CORE DE-HDL crashing often when launched from EDM Flow Manager
4 N! r, Q1 |7 T+ u2041145 CONCEPT_HDL CORE Set font size & color of netgroup names and netgroup taps
- i% p8 Q" q" ?! i2056743 CONCEPT_HDL CORE NetGroups appended with _1_1, some are empty, and inconsistent in DE-HDL CM and Allegro PCB Editor CM
0 u! A- |1 t) s) h/ O6 q2065889 CONCEPT_HDL CORE DE-HDL Modify command moves location of attached symbol properties! d: m3 Y, {/ L5 \8 g* H R
2074410 CONCEPT_HDL CORE Full net connectivity not shown in Allegro PCB Editor.
0 A+ w1 [3 B/ g- `' N2045717 CONCEPT_HDL RF_LAYOUT_DRI The RF PCB Options is greyed out when doing Import Physical on Linux with enterprise licenses
7 d* p. t; Y! E- U2045274 CONSTRAINT_MGR CONCEPT_HDL Running SKILL script or navigating pages in the hierarchy viewer crashes schematic editor! }6 v6 S$ ?7 J
2050521 CONSTRAINT_MGR OTHER Unexpected Xnet removal from schematic when Export to PCB Layout is executed.
9 g, j, Z! \$ j$ x2066270 PCB_LIBRARIAN SYMBOL_EDITOR Unable to edit note text containing comma
! L6 S7 B* _( m N4 B2069181 PCB_LIBRARIAN SYMBOL_EDITOR Pinlist window expand/collapse buttons act weird first time when invoked.) J" z; U* X0 ~, w
2070007 PCB_LIBRARIAN SYMBOL_EDITOR Project not found error in Symbol Editor when path contains space character
- `: g9 z: u% ^! k2072793 PCB_LIBRARIAN SYMBOL_EDITOR Right-click menu of formatting text objects is not consistent: second and third options are swapped4 U: |- J6 Y/ O$ P. Q' f
2073138 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor: Do not allow duplicate properties% \6 {+ W: R: p# N7 p
1957458 PSPICE FRONTENDPLUGI Refresh issue with Bias Display on a new design: bias value not updated
, u- c) d6 f2 T1 l: M/ ?2022211 PSPICE FRONTENDPLUGI Bias Point results are not updated
# E1 a" u% q; o9 x* B3 R Z5 E2031058 PSPICE FRONTENDPLUGI PSpice bias values are not getting updated
. n) ]; Q- o2 F, v/ T8 o% L% q2038021 PSPICE FRONTENDPLUGI Bias display is not updated
0 c+ q0 s& B4 c- c! n1 M2055274 PSPICE FRONTENDPLUGI Capture crashes on SIMSETUP OK when two projects are open* j }4 L7 }+ x' ^
2053432 RF_PCB OTHER Property on RF component not transferred to new design not containing the component) R% m# y; }3 T2 B* k# w1 y
2003341 SCM SCHGEN Unable to generate a schematic for hierarchical blocks' w7 L6 ?4 D( m* w
2069924 SIP_LAYOUT DIE_ABSTRACT_ Conversion from co-design die to standard die / BGA / anything else must remove floating function pins.0 y1 ^/ t( E, E- s
2067894 SIP_LAYOUT OTHER sip database size is enormous for a small component definition used in fdesign$ F0 I- R) d3 ~; ^% U4 }
2067987 SIP_LAYOUT OTHER Orphaned die attachment in SiP Layout cannot be removed
( w# I; B q2 L/ R, u2072857 SIP_LAYOUT OTHER SiP Layout crashes when using Find by Query and choosing 'Symbols'! D7 G, @1 I! h' o( |6 ?1 Z
2068973 SIP_LAYOUT REPORTS SiP Layout Missing Fillet report not catching a missing fillet in HotFix 051 and 052- w. P7 }- w& [+ y
2059533 SIP_LAYOUT SYMB_EDIT_APP SiP Layout: Cannot rotate bumps in Symbol Editor application mode
: N6 c$ c- d/ Q$ z @9 M1981749 SYSTEM_CAPTURE ARCHIVER System Capture: Archiving a design from the Tcl command window results in error9 C6 @ b$ H5 s1 h! S3 T
2054869 SYSTEM_CAPTURE AUTOMATION syscapUtils.tcl command cnsAutoCreateDiffPair is broken due to missing acm_code.il and acm_config.txt files
. p" ?3 ]+ z: P0 U$ c' C4 o1966488 SYSTEM_CAPTURE CANVAS_EDIT New folder rename box does not show the text typed.& @) M& a& @' F6 V- R5 d1 [
1814813 SYSTEM_CAPTURE COMPONENT_BRO System Capture session log should specify the CDSSITE path for the current session
6 \# h5 v/ F7 K9 m+ Y1977673 SYSTEM_CAPTURE COMPONENT_BRO adding reference blocks through add component error when cell name matches design name
* t# \) w$ t+ n9 e2 m' B2027100 SYSTEM_CAPTURE COMPOSITE_FIL pstdedb.cdsz and netlist preview in System capture is not being updated when individual netlist files are written
0 I. A# m8 P- g" \, x1961274 SYSTEM_CAPTURE CONNECTIVITY_ Xnet removed during pin swapping
6 s N( Y+ s* {! U1 p1 D) p+ C5 o2041879 SYSTEM_CAPTURE CONNECTIVITY_ xnets on net with only pull-up resistor
5 C0 Y6 ~7 `* O: r, d! U1889238 SYSTEM_CAPTURE COPY_PASTE Wire fails to connect during copy and paste
9 L, f" M! n0 j1993146 SYSTEM_CAPTURE DESIGN_EXPLOR Cannot move page up by only one position
/ t3 a' D k' A$ R+ n& J1910941 SYSTEM_CAPTURE MISCELLANEOUS Parts that are not in any schematic page appear in netlsit and BOM
) w0 R( ]+ ?* |- }8 A1902347 SYSTEM_CAPTURE PRINT Prints all sheets if one sheet is specified as the print range! v" l" D; F5 `- ~0 L2 V
2041272 SYSTEM_CAPTURE SMART_PDF Smart pdf displays component outline when component is not de-highlighted.
7 g; U/ q$ f. w+ B2065768 SYSTEM_CAPTURE SMART_PDF Custom Variable in Table Object not getting passed to PDF. X6 e! M; R! ^( j z
1969243 SYSTEM_CAPTURE VARIANT_MANAG Export variant does not name file correctly if the filename contains a space
2 F/ h. \7 S) B# @0 C5 Q6 b) T, P9 S1990258 SYSTEM_CAPTURE VARIANT_MANAG Cannot paste copied preferred part to multiple parts with the same part number: }7 m: ?9 |+ X* i5 ?% a7 d. d
1992250 SYSTEM_CAPTURE WORKSPACE Double-clicking a .CPM file runs System Capture but does not open project |
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