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3.1.2 Register Set
0 p( i& p/ t2 L @9 W9 TEach interface defines a register set that is mapped into various PCI address spacetypes. In addition to the registers required by the PCI specification, registers that mapinto the PCI Configuration Space, there are registers that are defined to describe andcontrol the device itself. These latter registers map into the PCI/PCIe bus addressspace which are in turn mapped into the system’s address space. These register setscan be grouped into,4 |1 | G/ I$ ]9 N0 { T
Capabilities Registers) X8 T( L, Y; K9 ]
Configuration Registers' F7 L, ]. p7 |7 H, q
Status Registers- B: W% g+ h0 N% b' d' c
Registers of these types exist in both interfaces. They allow the user to configureoperational aspects of the device, provide status on the device and to operate accesschannels to the storage extents within the various device domains.3 E6 L7 T! x$ D$ L9 F9 r
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* t0 g# B1 n Y6 `3.1.3 Queuing Layer
j* q3 C" a* O2 n' D6 U' ]0 C. LMost interfaces use queues for moving commands, command status and/or data acrossthe transport. Queues are typically used for smoothing the flow of information and data,functioning as elasticity buffers, and possibly maintaining command ordering of sometype. They provide the buffers needed for temporary storage of command andcommand status until they can be processed by the host or device.4 v( k/ {2 k* i& Z, N- n$ x5 l
Queuing layers must have usage rules associated with them. The mechanisms used toupdate queue head and tail pointers and notifications of when a queue has beenupdated to interested parties are all part of the queuing layer and its associatedprotocols.0 U6 i% Z' N7 O" B+ k. \
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