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Hyperlnyx中仿真，U1芯片为XCZU11EG-2FFVC1760E，- }) ~/ k, q) H- V
使用IBIS模型为zynquplus.ibs
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[IBIS ver] 5.1( f% Y6 g5 N. L3 G# H" j
[File name] zynquplus.ibs8 ~$ h" z, `% c- K. q
[File Rev] 1.12
% p6 ~1 y' w% p. {3 ]' G$ K' J# V( t[Date] 22-MARCH-20189 Z( W- ]9 J$ Y* F
[Source] Derived from spice models, rev1.0, using
9 {) _ [+ Y; h0 t+ u* W4 q hspice 2014.09-SP1-28 e9 [' l4 [6 I+ V7 n
[Notes] Xilinx IBIS file for Zynq UltraScale Plus I/O standards.
& \. Q2 H. O! B0 Z+ Z1 q0 k All models are preliminary.2 g, S4 @" a2 f T! u' P }
The version of IBISCHK used is ibischk5 V6.0.1.2 D! m4 L8 {( J
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[Disclaimer] The data in this file is derived from SPICE simulations using4 }+ o: @; A3 v% H8 g9 D
modeling information extracted from the target process. While$ [) K4 e: ]" C) t h9 {
a great deal of care has been taken to provide information
5 {5 g, s4 ]+ ? that is accurate, this model is considered preliminary as it
4 P- b4 K( \3 q# V has not been verified by actual silicon measurement. Treat the
! M6 ^) b, U R data in this model as preliminary until actual silicon, s: ]; l# M! P" }7 W; t; v
verification is peRFormed.
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9 j5 W' E; y% S[Copyright] Copyright 2016, Xilinx Inc., All rights reserved
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仿真的时候报错如图，请问各位朋友这个该怎么解决啊？3 j+ S4 V% Z+ W( _! b: @5 s
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发表于 2018-10-18 12:42
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