新手，求大神指点这段VHDL代码错来哪儿？

624132806

library ieee;
use ieee.std_logic_1164.all;
3 B& ?/ ~* j' y3 w8 V: Z+ P: E8 Dentity d_top is
port(d,lcr,lck: in std_logic;
q: out std_logic);
! b- P  z& c9 U7 |. R) ~/ Mend d_top;
architecture dd_top of d_top is
+ t; S0 S3 R& Rbegin
, i  Z7 i8 H7 _$ F0 p5 p  process(lcr,lck)
  begin
    if (lcr='0') then
      q<='0';
4 {6 X$ Q, T2 v# m* n2 G' I8 O' P    elseif (lck'event and lck='1') then
      q<=d;
' W6 I/ a  R2 g" t! |    end if;
- m) r( O" ]0 f, h6 d4 E: r  end process;
end dd_top;
) c; a! q2 H8 d2 k$ P. D+ j