求Cadence SPB16.2 Hotfix

gr1x

! D. t" Q; a# b% f8 i! t# V
. Q) u4 a/ t3 [+ Z) STLF有了cadence SPB16.2 Hotfix。但级别太低，老连不上服务器，下不下来。谁有呢？分享一下？？
2 K6 P" D! s+ D7 s1 {
: t# S. F1 l% P" h2 v已上传至Cadence_SPB16.2_by_dzkcool目录下。
20 Dec 2008 SPB16.20.001, Version: SPB:Hotfix:16.20.001~wint
- t0 T4 J, e0 S! L% R7 M打了补丁后记得要重新用nolic破解一遍。

HOTFIX VERSION:  001
========================================================================================================
CCRID      PRODUCT          PRODUCTLEVEL2        TITLE
# Z8 O! z9 c1 i7 j' s========================================================================================================
1 v9 N9 u. s- h% ^; @& V191020     allegro_EDITOR   SHAPE                Shape edits results in same net DRC being reported.
  m1 c# \9 D& I% D230469     ALLEGRO_EDITOR   SHAPE                Allegro improve peRFormance of Dynamic Shapes
* }5 U+ U" S* a; u: C9 h295039     ALLEGRO_EDITOR   DFA                  Allegro DFA to be enhanced to include height
346863     CIS              DESIGN_VARIANT       Variant View mode is not working for multi-section parts
. w% F! m* ~' z: u$ Y/ k400036     concept_HDL      HPF                  nihongo_vector_font should be listed in the Plot Setup GUI
410092     CONCEPT_HDL      OTHER                The Imported sheets loses the write permission for the group
415462     CONCEPT_HDL      MARKERS              The SPB157 Markers does not normally display the Japanese fon
- C4 K. C3 Q; ^, W5 G- a/ M501802     ALLEGRO_EDITOR   GRAPHICS             When hilighting parts or nets the system is inconsistent on z
503526     SPIF             OTHER                SPIF is NOT defining class for class to class rules.
* l- ]% s  H9 l, U# o511175     CONCEPT_HDL      CORE                 Copy All causes - No object selected error
+ V1 \# O5 _/ k! Y526774     LIBRARY          DEVELOPER            Pin抯 text size goes back to default size after change pin na
, }+ ?. H* c9 Q0 e: M533536     CONCEPT_HDL      OTHER                The font used in published PDF is not identical.
0 U6 g0 K2 m7 R3 @, v0 d2 s& w537769     CONCEPT_HDL      CORE                 Sporadic behavior of DE HDL toolbars for adding components ge
9 _6 B5 R, F) p; Q9 T3 E! Y7 V544519     ALLEGRO_EDITOR   mentor               mbs2lib Generating extra "b" version of footprint during tran
! a) u% d$ M! |0 c551528     LAYOUT           OTHER                Layout2Allegro L2A translator not translating reference desig
+ t& p) p; l3 p* @+ Q  z; m0 j551614     SIG_INTEGRITY    IRDROP               Import and export of IR-Drop setup
552127     LIBRARY          LIBUTIL              When -lib is missing from con2con PTF files get re-written in
560417     ALLEGRO_EDITOR   OTHER                Part Logic does not read part row from ptf file and assign in
564954     CONCEPT_HDL      CREFER               Crefer attaches $XR property to other $XR on RHEL.
8 j1 p5 O! P! o  U: p565798     CIS              DESIGN_VARIANT       all the sections of mult part package are not coming as DNS i
571627     CONCEPT_HDL      CONSTRAINT_MGR       cmuprev fails to synchronize constraints on low assertion vec
( b& S, n4 M; n0 j' [$ j0 t577915     CONCEPT_HDL      ARCHIVER             zero folder is not archived how the archiver is working ?
581446     LAYOUT           TRANSLATION          L2A fails with pin numbers do not match between symbols from
583891     ALLEGRO_EDITOR   MENTOR               Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
0 \$ q  I% _' l: l" F3 v( b586998     ALLEGRO_EDITOR   PLOTTING             Board shifts towards top left when plotting at higher resolut
9 E1 v2 S) s2 N8 t0 y587870     ALLEGRO_EDITOR   PCAD_IN              Import PCAD fails due to dupliate pad name.  Caused by a peri
588949     CONCEPT_HDL      CORE                 Importing schematic pages from another project crashes Concep
592340     ALLEGRO_EDITOR   MENTOR               MBS2LIB not creating the correct shape in symbol
: |; L9 e6 G, x3 O596530     ALLEGRO_EDITOR   pads_IN              PADS to Allegro Translator removing/renaming reference design
596638     ALLEGRO_EDITOR   EDIT_ETCH            The timing meter indicates untruthful violation
596716     Pspice           DEHDL                Flag error due to part pin mismatch while create netlist
597685     ALLEGRO_EDITOR   SCHEM_FTB            ratnest are out of date error in DBDoctor after import logic
$ k7 `# t+ o- Q' S- x2 f! o2 X597937     ALLEGRO_EDITOR   PADS_IN              Request PADs_in to translate keepout areas
% Y& J) `& M& e& L) [7 |598575     ALLEGRO_EDITOR   OTHER                During Split plane should it use settings regarding fill styl
598814     APD              WIREBOND             bondfinger does not move relative to its origin using ipick
4 q# y$ e9 @- [) T9 U! i$ U599823     CONCEPT_HDL      CONSTRAINT_MGR       Lost ref to dml-lib causes loss of cm data even if the refere
; F7 ~% D: D- ?. h599886     APD              EXPORT_DATA          bodygen batch tool is failing to generate .css file
$ v! y! l6 H' j: S1 Z603425     SPECCTRA         PARSER               Do file fails Syntax error in command unexpected end-of-line
603987     APD              OTHER                Offset via generator should ensure pitch distance is met or e
/ d" e3 J# Q2 w+ R* I) u% k604377     SCM              PACKAGER             Output board name containing a dash causes scm crash
1 l: E, K4 T- P& {5 A7 g! z, x604614     CONSTRAINT_MGR   OTHER                netrev is unable to update the Canonical paths with the new d
604794     ALLEGRO_EDITOR   PAD_EDITOR           Replace Padstack reports error pad missing not true.
605169     ALLEGRO_EDITOR   OTHER                Can design_compare handle swappable pins?
* U4 M/ j8 S6 l9 [7 O6 D& X606586     ALLEGRO_EDITOR   INTERFACES           Multiple drill in padstack cannot be shown in Pro/E IDF
607217     APD              IO_PLANNER           wirebond die replacement from IOP
607222     APD              WIREBOND             auto wirebonding creates wirebond with DRC
/ g5 y1 |8 q1 E607644     ALLEGRO_EDITOR   MANUFACT             Enhancement to increase the IDF export ''default package heig
607718     CONCEPT_HDL      HDLDIRECT            HDL Direct Errors reported while generating simulation netlis
/ Y) k) I" p) B0 U608233     SIG_INTEGRITY    FIELD_SOLVERS        Convergence errors with analytical vias when drill size is 1
609549     ALLEGRO_EDITOR   INTERACTIV           Mirror Geometry command to change BB Via's layer.
610028     SIP_LAYOUT       IMPORT_DATA          De assign NC nets during aif import
610134     CONSTRAINT_MGR   INTERACTIV           Cross-probing from CM to Allegro no longer works on system le
& w: l) r/ \+ A* B610276     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro translation is failing with error.
610482     ALLEGRO_EDITOR   SCHEM_FTB            Netlist swapped net names on 2 pins causing shape to lose its
610681     CONSTRAINT_MGR   DATABASE             An exported constraint file can not be re-imported in V16.01
611260     ALLEGRO_EDITOR   DRC_CONSTR           Routing a diff pair it does not follow Physical line width se
0 e1 I% x) R# ~8 _% J: [611425     ALLEGRO_EDITOR   MENTOR               mbs2brd crashes when importing Mentor
) j8 F0 k8 n. T. n3 e611697     SIP_FLOW         SIP_LAYOUT           octagonal bumps have offset in SIP compared to the chip view
611807     APD              WIREBOND             Duplicate paths created on wirebond import for some cases.
611856     CONCEPT_HDL      GLOBALCHANGE         Ref des deletions after runnning Global Change to change $LOC
611874     CONCEPT_HDL      OTHER                Crossprobing one symbol in Concept using Occurence edit mode
8 q9 o5 W% W3 u612088     PSPICE           DEHDL_NETLISTER      Fail to create the netlist for G value expression
612195     ALLEGRO_EDITOR   DATABASE             Adding layers to the default cross section causes phantom tex
612237     ALLEGRO_EDITOR   skill                axlFormColorize does not change the full background area of a
1 Z9 b. i! n: n7 ^612299     APD              DEGASSING            Degassing static shape creates voids inside of voided areas
612560     CONSTRAINT_MGR   OTHER                Diffpairs don't show the CSet assigned through Net Class
" P+ E: N8 Q/ K: ?0 A612587     APD              WIREBOND             Unchecked Allow DRC option creating disconnected wire bond.
9 [. b# x* w* l" j7 G6 X% |612884     SIG_INTEGRITY    SIMULATION           When using ViaModel
612914     ALLEGRO_EDITOR   EDIT_ETCH            Centered via option in fanout command not available when swit
612939     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Continuous Solder Mask check problem
$ g$ H6 ?( Q8 [9 z5 m6 ?2 Z3 {- u613553     CONCEPT_HDL      EDIF300              edif schematic writer crash on this design
613565     ALLEGRO_EDITOR   EDIT_ETCH            Allegro Editor Differential Pairs are routing incorrectly
613736     SPIF             OTHER                Spif fails to write class data
5 J8 F0 _7 x5 Y6 t2 n613990     POWER_INTEGRIT   INTERACTIV           PI is crashing during capacitor selection
$ `. [8 C/ r4 x$ G) W* A614278     CONCEPT_HDL      EDIF300              pin text note and flag are not visible on reloaded edif file
6 |0 y5 i2 m: j' E4 [* J614371     SIP_LAYOUT       WIREBOND             Any wirebond command crashes the application
* n& T: Z& D, b" l614407     POWER_INTEGRIT   INTERACTIV           PI crashes when editing capacitors
614727     SPECCTRA         GUI                  Allegro PCB Router can not process the dsn and rules file for
614972     ALLEGRO_EDITOR   SKILL                axlCNSSetSpacing does not change the value of the "testvia to
$ W7 t, ]; u# l4 ]- A8 ?615144     SIP_LAYOUT       3D_VIEWER            die placement does not change with changing in soldermask thi
8 w0 y7 \' ?3 V8 W1 l+ h; j615431     LAYOUT           TRANSLATORS          padstack names are crippled or renamed if it has over 18 Char
615506     APD              MANUFACTURING        Sort by die pin location for Manufacture Doc Bond finger brok
: S8 v+ O0 T; {' q, d/ j9 l, G615745     SIP_LAYOUT       DATABASE             Move die symbol with stretch etch on is disconnecting wires f
5 [, M) E6 j6 O4 W5 O- Z615816     SPIF             OTHER                Allegro match group members not translating to PCB Router; mi
! @2 \! `) Z) e0 _; [. P- d616104     CONSTRAINT_MGR   OTHER                allegroTechnologyFile XML format issue
616122     LAYOUT           TRANSLATORS          protel to MAX translator problem with package outlines and re
616404     ALLEGRO_EDITOR   OTHER                Design compare fails with message "Invalid input argument" wh
616713     CIS              PLACE_DATABASE_PAR   property name with "&" charecter in access database causing c
9 f& x9 K" E0 Z$ _616818     SCM              PACKAGER             BOMHDL -type scm fails on schematic block
4 M( U9 x2 S( v6 [# I/ o/ }616907     SCM              VERILOG_IMPORT       scm crash during Get Module Name
. _. ]  B4 h1 Z, w: G5 F  {617058     APD              WIREBOND             wirebond space evenly does not work for fingers on power ring
617083     ALLEGRO_EDITOR   INTERACTIV           Windows tabs hangs on Linux
617236     ALLEGRO_EDITOR   SHAPE                Editing a shape in a void causes the bigger shape to drop seg
" l5 X! m. ?& P* X3 `  o& H, e617351     CIS              DBC_CFG_WIZARD       XML writer fails if DBC location doesnt have write permission
617515     SIP_LAYOUT       OTHER                Be able to invoke Velocity from cdnsip
1 k+ }2 |+ X' p3 V) {$ x2 X" W617761     LAYOUT           TRANSLATORS          Value property for Library symbol of orcad Layout is not tran
% [8 I2 n! C% B" u5 C617890     SIP_LAYOUT       WIREBOND             Push and shove on Bond fingers with multiple bond wires cause
618184     APD              OTHER                database diary on unix/linux
# u6 V) G! f; t% R618201     ALLEGRO_EDITOR   OTHER                Dynamic fillets take a long time to complete
5 [, b0 z8 u% _* e/ X/ o- v: L618545     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes when we place a package symbol for Jumper usi
  k, F4 z6 R" q: N8 V% I8 }618610     ALLEGRO_EDITOR   MANUFACT             Delete a cline seg creates a fillet
$ d5 @3 M8 b9 d' V8 t3 X- F* ]618651     SIP_LAYOUT       IO_PLANNER           Bondfingers and die are shifted every time an update package
1 C7 }, h, x2 P, z& q8 P618712     ALLEGRO_EDITOR   EDIT_ETCH            Shove mode is not working on Diff pairs in PCB Design L
# z, ]. B+ v, D  o8 \! e618836     ALLEGRO_EDITOR   SCRIPTS              Allegro does not interpret recorded macro script files proper
3 p" M' m; I& o% ]: B4 B, [9 O( h. |618946     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes while using Place Manual -H
1 ~/ Y, X5 V! U- f  D- `: _618984     ALLEGRO_EDITOR   COLOR                Layers on Allegro Canvas does not match Color Dialog Box
619007     ALLEGRO_EDITOR   SKILL                Skill command does not accept spaces in file path/name
619033     F2B              PACKAGERXL           Pinswap lost on backannotation
1 K2 ^8 S. Z1 V; w& T2 q619268     POWER_INTEGRIT   SIMULATION           IR-Drop can't sees via on pad as open
619356     CIS              FOOTPRINT_VIEW       Footprint preview only from 1 directory in Capture.INI
619712     ALLEGRO_EDITOR   EDIT_ETCH            Unable to route in the Bubble Mode for Partitioned board
619773     ALLEGRO_EDITOR   DATABASE             Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
$ y  E" g; F6 b( a! i; b, O620064     CONCEPT_HDL      CONSTRAINT_MGR       Loosing Diff pair constraints from lower blocks when packagin
) N7 R4 u7 u, a* `. N+ y622132     CAPTURE          NETLIST_ALLEGRO      Incorrect ALG0078 error for complex hierarchical design

gr1x

原帖由 jxnfhyz 于 2008-12-30 10:32 发表
7 q* F! W  M; D3 l2 f5 ]! _TLF是什么哦,是不是指在FTP上啊!

www.eastgame.net

touhou

下到了SPB16.2 Hotfix的人路过

轩辕浪

软件还没出来几天，补丁就下来了？、、

zxfeng

分流
5 A+ R5 H. Z4 F% P6 v% NHotfix_SPB16.20.001_wint_1of1.exe (243.01 MB)

gr1x

原帖由 zxfeng 于 2008-12-30 15:40 发表
! Z! G" t* _; ]4 J. {, Y0 @分流
3 x+ S9 ?2 ?% y0 A3 I9 ]. fHotfix_SPB16.20.001_wint_1of1.exe (243.01 MB)

! P# B  c/ _1 [7 B8 N, m开了2天电脑，就下了30多k，谁能提供下载呢？

wanghanq

原帖由 jxnfhyz 于 2008-12-30 10:32 发表
' [7 U  V  {0 r% {( `  m6 S. [TLF是什么哦,是不是指在FTP上啊!

. i( [  p$ P4 |看下面链接，你就知道了，里面的资源太多了：

3 m$ K7 f6 S/ Q0 I4 S: h4 j5 G2 T6 A
- s2 L0 k# L( I9 K! Dhttp://www3.eastgame.net/index.php

zxfeng

开了2天电脑，就下了30多k，谁能提供下载呢？
gr1x 发表于 2008-12-31 20:45

7 V0 t, w+ X0 N, Q* M我看到至少有三个人完成下载了，emule下载需要耐心.

rx_78gp02a

下载了的可以用qq或者是邮箱传一下的嘛！速度很快的，今天误删了license server 重新安装上去就不能用了

zhuyt05

我看到至少有三个人完成下载了，emule下载需要耐心.
$ n# p% q, `& o: q" f4 Z/ rzxfeng 发表于 2009-1-3 15:32

* D2 N$ w3 r3 A
0 p# w+ @$ s9 b0 D* d1 U这三个人中有一个是我，改天帮助大家加速

zlei

我就是在tlf的S15服务器下的。

DANYEHUA

DDD