求Cadence SPB16.2 Hotfix

gr1x

3 t+ L1 @/ x5 Q9 `, u( ^
TLF有了cadence SPB16.2 Hotfix。但级别太低，老连不上服务器，下不下来。谁有呢？分享一下？？
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7 W) ]4 G8 K$ D& q已上传至Cadence_SPB16.2_by_dzkcool目录下。
/ A3 i% i( D8 \& u- M: L20 Dec 2008 SPB16.20.001, Version: SPB:Hotfix:16.20.001~wint
# |6 [1 ^3 R# A- x2 i" q; a' K6 [打了补丁后记得要重新用nolic破解一遍。
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2 C5 h. |- A8 N- z6 ]3 WHOTFIX VERSION:  001
! s/ I) W; M7 N' @8 P' M========================================================================================================
1 H) f% K) M/ ECCRID      PRODUCT          PRODUCTLEVEL2        TITLE
8 b3 E) @$ m3 ?) a8 A========================================================================================================
191020     allegro_EDITOR   SHAPE                Shape edits results in same net DRC being reported.
230469     ALLEGRO_EDITOR   SHAPE                Allegro improve peRFormance of Dynamic Shapes
295039     ALLEGRO_EDITOR   DFA                  Allegro DFA to be enhanced to include height
+ R, a' S6 u/ i/ C9 W& _9 q346863     CIS              DESIGN_VARIANT       Variant View mode is not working for multi-section parts
, e( @  s7 W2 T, D5 I8 X400036     concept_HDL      HPF                  nihongo_vector_font should be listed in the Plot Setup GUI
4 _7 T4 \$ _- K% j7 ~, ?410092     CONCEPT_HDL      OTHER                The Imported sheets loses the write permission for the group
5 @/ k! Z. Y% }8 H415462     CONCEPT_HDL      MARKERS              The SPB157 Markers does not normally display the Japanese fon
4 W* ?0 c: w' n) m501802     ALLEGRO_EDITOR   GRAPHICS             When hilighting parts or nets the system is inconsistent on z
; E) \2 m  N: [' `& Q503526     SPIF             OTHER                SPIF is NOT defining class for class to class rules.
511175     CONCEPT_HDL      CORE                 Copy All causes - No object selected error
- B8 R3 c$ k( _526774     LIBRARY          DEVELOPER            Pin抯 text size goes back to default size after change pin na
  _9 {5 c; F+ Q( }, d533536     CONCEPT_HDL      OTHER                The font used in published PDF is not identical.
537769     CONCEPT_HDL      CORE                 Sporadic behavior of DE HDL toolbars for adding components ge
% r/ l/ C$ C3 g4 d544519     ALLEGRO_EDITOR   mentor               mbs2lib Generating extra "b" version of footprint during tran
  W7 r% @. K  n( e3 j( c  m551528     LAYOUT           OTHER                Layout2Allegro L2A translator not translating reference desig
551614     SIG_INTEGRITY    IRDROP               Import and export of IR-Drop setup
- W9 h; {5 `& R! J+ o$ S+ ]552127     LIBRARY          LIBUTIL              When -lib is missing from con2con PTF files get re-written in
560417     ALLEGRO_EDITOR   OTHER                Part Logic does not read part row from ptf file and assign in
564954     CONCEPT_HDL      CREFER               Crefer attaches $XR property to other $XR on RHEL.
565798     CIS              DESIGN_VARIANT       all the sections of mult part package are not coming as DNS i
2 \  `4 G( u) J; N' ~8 k571627     CONCEPT_HDL      CONSTRAINT_MGR       cmuprev fails to synchronize constraints on low assertion vec
577915     CONCEPT_HDL      ARCHIVER             zero folder is not archived how the archiver is working ?
581446     LAYOUT           TRANSLATION          L2A fails with pin numbers do not match between symbols from
583891     ALLEGRO_EDITOR   MENTOR               Mbs2brd will not run with PA5630 license (Allegro PCB SI GXL)
586998     ALLEGRO_EDITOR   PLOTTING             Board shifts towards top left when plotting at higher resolut
4 o5 O9 _' k& e/ @9 P# z  W587870     ALLEGRO_EDITOR   PCAD_IN              Import PCAD fails due to dupliate pad name.  Caused by a peri
9 p, B& x  ^; y: C1 g& t588949     CONCEPT_HDL      CORE                 Importing schematic pages from another project crashes Concep
- o* G0 |0 a# ~" A' k$ p; G592340     ALLEGRO_EDITOR   MENTOR               MBS2LIB not creating the correct shape in symbol
596530     ALLEGRO_EDITOR   pads_IN              PADS to Allegro Translator removing/renaming reference design
2 Y8 a0 ~6 E; F( p6 Q596638     ALLEGRO_EDITOR   EDIT_ETCH            The timing meter indicates untruthful violation
9 g, h% f! v- g2 t+ N' x596716     Pspice           DEHDL                Flag error due to part pin mismatch while create netlist
597685     ALLEGRO_EDITOR   SCHEM_FTB            ratnest are out of date error in DBDoctor after import logic
: X. j- l0 F0 P$ I597937     ALLEGRO_EDITOR   PADS_IN              Request PADs_in to translate keepout areas
2 n' P2 D9 y5 c! [) F& b598575     ALLEGRO_EDITOR   OTHER                During Split plane should it use settings regarding fill styl
598814     APD              WIREBOND             bondfinger does not move relative to its origin using ipick
599823     CONCEPT_HDL      CONSTRAINT_MGR       Lost ref to dml-lib causes loss of cm data even if the refere
- j) V; E" H, E3 M0 P5 H/ y599886     APD              EXPORT_DATA          bodygen batch tool is failing to generate .css file
/ q- Q5 N& [& d7 Q603425     SPECCTRA         PARSER               Do file fails Syntax error in command unexpected end-of-line
/ P* {* k$ @1 p( b3 l1 C603987     APD              OTHER                Offset via generator should ensure pitch distance is met or e
604377     SCM              PACKAGER             Output board name containing a dash causes scm crash
604614     CONSTRAINT_MGR   OTHER                netrev is unable to update the Canonical paths with the new d
6 i% m- j  b! r; V& c/ m+ Q% a5 t6 y604794     ALLEGRO_EDITOR   PAD_EDITOR           Replace Padstack reports error pad missing not true.
605169     ALLEGRO_EDITOR   OTHER                Can design_compare handle swappable pins?
( Z8 T0 U3 s* a* h606586     ALLEGRO_EDITOR   INTERFACES           Multiple drill in padstack cannot be shown in Pro/E IDF
607217     APD              IO_PLANNER           wirebond die replacement from IOP
8 o9 C& _' k( y% [& C- w7 o9 A607222     APD              WIREBOND             auto wirebonding creates wirebond with DRC
607644     ALLEGRO_EDITOR   MANUFACT             Enhancement to increase the IDF export ''default package heig
607718     CONCEPT_HDL      HDLDIRECT            HDL Direct Errors reported while generating simulation netlis
7 N) m/ d! p* H5 |: i608233     SIG_INTEGRITY    FIELD_SOLVERS        Convergence errors with analytical vias when drill size is 1
609549     ALLEGRO_EDITOR   INTERACTIV           Mirror Geometry command to change BB Via's layer.
610028     SIP_LAYOUT       IMPORT_DATA          De assign NC nets during aif import
610134     CONSTRAINT_MGR   INTERACTIV           Cross-probing from CM to Allegro no longer works on system le
610276     ALLEGRO_EDITOR   PADS_IN              PADS to Allegro translation is failing with error.
610482     ALLEGRO_EDITOR   SCHEM_FTB            Netlist swapped net names on 2 pins causing shape to lose its
610681     CONSTRAINT_MGR   DATABASE             An exported constraint file can not be re-imported in V16.01
611260     ALLEGRO_EDITOR   DRC_CONSTR           Routing a diff pair it does not follow Physical line width se
611425     ALLEGRO_EDITOR   MENTOR               mbs2brd crashes when importing Mentor
611697     SIP_FLOW         SIP_LAYOUT           octagonal bumps have offset in SIP compared to the chip view
  N- C. e: I- l611807     APD              WIREBOND             Duplicate paths created on wirebond import for some cases.
611856     CONCEPT_HDL      GLOBALCHANGE         Ref des deletions after runnning Global Change to change $LOC
6 [3 e) E  }0 q4 E; T611874     CONCEPT_HDL      OTHER                Crossprobing one symbol in Concept using Occurence edit mode
, H6 P, ], l, H- I$ x! P612088     PSPICE           DEHDL_NETLISTER      Fail to create the netlist for G value expression
; m3 Z5 s+ A( K5 R7 R) A612195     ALLEGRO_EDITOR   DATABASE             Adding layers to the default cross section causes phantom tex
612237     ALLEGRO_EDITOR   skill                axlFormColorize does not change the full background area of a
! h; R6 w* I- T1 l% ]& R612299     APD              DEGASSING            Degassing static shape creates voids inside of voided areas
& q2 W) U% i; s' I( X612560     CONSTRAINT_MGR   OTHER                Diffpairs don't show the CSet assigned through Net Class
612587     APD              WIREBOND             Unchecked Allow DRC option creating disconnected wire bond.
612884     SIG_INTEGRITY    SIMULATION           When using ViaModel
: Z( u+ R! |3 ~$ b3 \612914     ALLEGRO_EDITOR   EDIT_ETCH            Centered via option in fanout command not available when swit
3 }" \' h0 _0 v) A( X612939     SIP_LAYOUT       ASSY_RULE_CHECK      ADRC Continuous Solder Mask check problem
613553     CONCEPT_HDL      EDIF300              edif schematic writer crash on this design
" ~  k' Q) ^. N" L; v0 W, k! ^. N613565     ALLEGRO_EDITOR   EDIT_ETCH            Allegro Editor Differential Pairs are routing incorrectly
  C- f  W. ]+ W. z4 S& Q613736     SPIF             OTHER                Spif fails to write class data
+ p& w8 }% ^( E6 ~% M' B613990     POWER_INTEGRIT   INTERACTIV           PI is crashing during capacitor selection
614278     CONCEPT_HDL      EDIF300              pin text note and flag are not visible on reloaded edif file
0 Y" P) c1 l/ R0 Q, ?" d614371     SIP_LAYOUT       WIREBOND             Any wirebond command crashes the application
4 Q' S! y! f' }$ }# Y3 A& Y614407     POWER_INTEGRIT   INTERACTIV           PI crashes when editing capacitors
614727     SPECCTRA         GUI                  Allegro PCB Router can not process the dsn and rules file for
6 e. z$ \. W5 t& E) U5 x/ `: [9 v614972     ALLEGRO_EDITOR   SKILL                axlCNSSetSpacing does not change the value of the "testvia to
615144     SIP_LAYOUT       3D_VIEWER            die placement does not change with changing in soldermask thi
615431     LAYOUT           TRANSLATORS          padstack names are crippled or renamed if it has over 18 Char
615506     APD              MANUFACTURING        Sort by die pin location for Manufacture Doc Bond finger brok
615745     SIP_LAYOUT       DATABASE             Move die symbol with stretch etch on is disconnecting wires f
615816     SPIF             OTHER                Allegro match group members not translating to PCB Router; mi
616104     CONSTRAINT_MGR   OTHER                allegroTechnologyFile XML format issue
# n% y; X/ V$ i) [! Z6 b1 W616122     LAYOUT           TRANSLATORS          protel to MAX translator problem with package outlines and re
# l) v' E4 q" \$ k$ e616404     ALLEGRO_EDITOR   OTHER                Design compare fails with message "Invalid input argument" wh
! Z% P' E8 [* s" U5 y: @( U1 k616713     CIS              PLACE_DATABASE_PAR   property name with "&" charecter in access database causing c
1 _; J7 ~" O4 h6 g, x4 q616818     SCM              PACKAGER             BOMHDL -type scm fails on schematic block
7 q9 t- v. Y. d# R$ p) @8 j616907     SCM              VERILOG_IMPORT       scm crash during Get Module Name
" s+ [* I; G$ k$ W617058     APD              WIREBOND             wirebond space evenly does not work for fingers on power ring
617083     ALLEGRO_EDITOR   INTERACTIV           Windows tabs hangs on Linux
617236     ALLEGRO_EDITOR   SHAPE                Editing a shape in a void causes the bigger shape to drop seg
$ D1 \* R! |; v: b3 _! ]) I7 f  l617351     CIS              DBC_CFG_WIZARD       XML writer fails if DBC location doesnt have write permission
617515     SIP_LAYOUT       OTHER                Be able to invoke Velocity from cdnsip
617761     LAYOUT           TRANSLATORS          Value property for Library symbol of orcad Layout is not tran
617890     SIP_LAYOUT       WIREBOND             Push and shove on Bond fingers with multiple bond wires cause
618184     APD              OTHER                database diary on unix/linux
! L0 r2 J; ^5 |; y  y' W6 r618201     ALLEGRO_EDITOR   OTHER                Dynamic fillets take a long time to complete
618545     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes when we place a package symbol for Jumper usi
618610     ALLEGRO_EDITOR   MANUFACT             Delete a cline seg creates a fillet
618651     SIP_LAYOUT       IO_PLANNER           Bondfingers and die are shifted every time an update package
0 @- ^! v: x% l- V618712     ALLEGRO_EDITOR   EDIT_ETCH            Shove mode is not working on Diff pairs in PCB Design L
618836     ALLEGRO_EDITOR   SCRIPTS              Allegro does not interpret recorded macro script files proper
, o' Y# C0 T4 f" m618946     ALLEGRO_EDITOR   INTERACTIV           Allegro crashes while using Place Manual -H
618984     ALLEGRO_EDITOR   COLOR                Layers on Allegro Canvas does not match Color Dialog Box
& H3 l9 H/ u5 q9 {! T* f7 G619007     ALLEGRO_EDITOR   SKILL                Skill command does not accept spaces in file path/name
619033     F2B              PACKAGERXL           Pinswap lost on backannotation
619268     POWER_INTEGRIT   SIMULATION           IR-Drop can't sees via on pad as open
619356     CIS              FOOTPRINT_VIEW       Footprint preview only from 1 directory in Capture.INI
* H8 n" L* x' C9 A0 r/ M/ i& S619712     ALLEGRO_EDITOR   EDIT_ETCH            Unable to route in the Bubble Mode for Partitioned board
" G5 Y/ w. ]/ m$ H619773     ALLEGRO_EDITOR   DATABASE             Uprev for 13.6 and 14.0 files not working with SPB 16.2 on Wi
& W+ T3 ^7 q9 d620064     CONCEPT_HDL      CONSTRAINT_MGR       Loosing Diff pair constraints from lower blocks when packagin
3 T  w9 Y: l/ n/ h622132     CAPTURE          NETLIST_ALLEGRO      Incorrect ALG0078 error for complex hierarchical design

gr1x

原帖由 jxnfhyz 于 2008-12-30 10:32 发表
1 N2 O& ]7 A8 z" P) `+ ]TLF是什么哦,是不是指在FTP上啊!

www.eastgame.net

touhou

下到了SPB16.2 Hotfix的人路过

轩辕浪

软件还没出来几天，补丁就下来了？、、

zxfeng

分流
+ ]+ F2 }5 k. U* \- ^- LHotfix_SPB16.20.001_wint_1of1.exe (243.01 MB)

gr1x

原帖由 zxfeng 于 2008-12-30 15:40 发表
分流
+ s+ p$ D  m3 K1 c: Y) G! O; bHotfix_SPB16.20.001_wint_1of1.exe (243.01 MB)

开了2天电脑，就下了30多k，谁能提供下载呢？

wanghanq

原帖由 jxnfhyz 于 2008-12-30 10:32 发表
TLF是什么哦,是不是指在FTP上啊!

( S3 B1 c/ l& N
看下面链接，你就知道了，里面的资源太多了：
& ~/ x4 A% r0 j9 @  p5 X. ]$ v2 r: F2 C

http://www3.eastgame.net/index.php

zxfeng

开了2天电脑，就下了30多k，谁能提供下载呢？
gr1x 发表于 2008-12-31 20:45

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我看到至少有三个人完成下载了，emule下载需要耐心.

rx_78gp02a

下载了的可以用qq或者是邮箱传一下的嘛！速度很快的，今天误删了license server 重新安装上去就不能用了

zhuyt05

我看到至少有三个人完成下载了，emule下载需要耐心.
zxfeng 发表于 2009-1-3 15:32

7 _! M# ?& s; E2 M这三个人中有一个是我，改天帮助大家加速

zlei

我就是在tlf的S15服务器下的。

DANYEHUA

DDD