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不方便截图,这是新找到的,是17.2的问题
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1.Close the design if it is open in Allegro PCB Editor.: Q; N7 J7 \: k- u' Z' @4 j3 v
2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.
( @# Y, _- _5 c& r' v: H3.Open the design in Allegro PCB Editor.
0 Y. b4 r2 x o. U4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.' }' U7 Y3 d- ?. O4 Q2 c
5.Open Constraint Manager.* y: j# n5 Y* W' F( y1 h# ^- d
6.Select Tools > Options.
. n0 U) y$ n, w! A: T7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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