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不方便截图,这是新找到的,是17.2的问题
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1.Close the design if it is open in Allegro PCB Editor.
K1 T0 D: @2 ^7 w- i! [, |2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.& N4 F5 E! {4 k+ f8 H: B
3.Open the design in Allegro PCB Editor.' B9 U5 I s( P5 e: L% z8 x) n
4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.; }5 m+ x0 } J+ a3 S- N7 u
5.Open Constraint Manager.
0 h. G. H6 s/ R7 v. P4 W6.Select Tools > Options.' f. a9 j [, j0 n, M
7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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