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不方便截图,这是新找到的,是17.2的问题3 {# `: U0 K* {) R
, @7 ~4 a- L1 f* p1.Close the design if it is open in Allegro PCB Editor.$ {. i: \ I0 e4 d X
2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.
. v& x* K* U% `$ v/ b4 C' q3.Open the design in Allegro PCB Editor.0 n' h0 L1 ?# V9 ^( R& \( N, Q
4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL. Z: ~& F$ ?* k. r+ q1 |( W
5.Open Constraint Manager. N9 f5 Q5 u8 o) x
6.Select Tools > Options.& ^& M: x7 e1 ^
7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
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