|
不方便截图,这是新找到的,是17.2的问题
/ X$ L! A& l* F# P4 L2 Y# ~" {
* ~( T: `) ^9 o* z1.Close the design if it is open in Allegro PCB Editor.
2 i" s, ~$ x. `. T7 g4 x2.Add the CDS_XNET_STATE_UI variable with a value of 1 to the User variables section in the Environment Variables form.) X% P: X. k. G' n5 w) v! E
3.Open the design in Allegro PCB Editor. p0 Y" v; O" g, Y
4.Go to File > Import > Logic and, if not already set, set the Import Logic Type to Design Entry HDL.
) f( D1 T: x# p5.Open Constraint Manager.
0 @* h$ V3 A/ v# d! V2 v6.Select Tools > Options. f* ~* l2 y3 J o
7.Select the Create XNets and Differential Pairs using DML Models (same as SPB 16.6) option. |
|