SystemVerilog for Verification

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/ P7 W" _- p% ]( Q1 X+ g$ k& A1 ASystemVerilog for Verification:
A Guide to Learning the Testbench Language Features
) {1 _. g& R0 S" K! I: e1. VERIFICATION GUIDELINES 1
- U# Z4 K. j+ m! e) C( r1.1 Introduction 1
; x/ h$ w4 h% X1.2 The Verification Process 2
# x' Z. i. D/ D% U1.3 The Verification Plan 4
1.4 The Verification Methodology Manual 4
1 z' v" O' w' m. e+ k) V: d1.5 Basic Testbench Functionality 5
1.6 Directed Testing 5
" [  B( }8 V$ O- n7 A1.7 Methodology Basics 7
8 ^( K/ H& q' C/ h. x& v; `1.8 Constrained-Random Stimulus 8
1.9 What Should You Randomize? 10
" C3 \+ U( ?2 a1.10 Functional Coverage 13
  b( {  s( H0 b7 u; V3 R7 ]1.11 Testbench Components 15
2 Z& i9 }0 ?9 p3 @: r3 f# {1.12 Layered Testbench 16
9 w& R* n3 n6 m1.13 Building a Layered Testbench 22
1.14 Simulation Environment Phases 23
; \! t: e9 T1 k. r+ f8 M' b$ W2 S1.15 Maximum Code Reuse 24
) ]* }$ A6 w' e/ w$ y$ e" a5 M$ s) }7 h1.16 Testbench PeRFormance 24
1.17 Conclusion 25
2. DATA TYPES 27
' c8 E# z1 Q/ j% B2 b* _* d2.1 Introduction 27
$ E5 R* f  g* e+ F; j( f1 f' v2.2 Built-in Data Types 27
+ k# @. i: k/ @7 ~1 x6 E. qviii SystemVerilog for Verification
% y9 X# o* e: T  h% \3 n0 S2 ]2.3 Fixed-Size Arrays 29
/ _( p) N5 K& Z2.4 Dynamic Arrays 34
2.5 Queues 36
2.6 Associative Arrays 37
2.7 Linked Lists 39
2.8 Array Methods 40
3 _" S; v1 E5 ?; R1 U7 v2.9 Choosing a Storage Type 42
5 l. W, T9 l+ T( x  R2.10 Creating New Types with typedef 45
2.11 Creating User-Defined Structures 46
2.12 Enumerated Types 47
: `( |8 M" L9 b: P  ~2.13 Constants 51
9 u" e5 _2 P; f  E" f: I2.14 Strings 51
  M0 H3 i' \2 ?% k- ^2.15 Expression Width 52
3 ]: |8 M9 d+ G! E" H# d4 I) A& N) X2.16 Net Types 53
2.17 Conclusion 53
. d* k; ?2 g" X& o/ Y* F7 _3. PROCEDURAL STATEMENTS AND ROUTINES 55
& r8 x: X5 U, p* A+ |) D- u3.1 Introduction 55
1 L7 e7 D% a% v+ @. E3.2 Procedural Statements 55
3.3 Tasks, Functions, and Void Functions 56
; b9 t, k+ C  b1 ^8 O3.4 Task and Function Overview 57
3.5 Routine Arguments 57
8 U) r, u! @3 L8 s' f1 M  R3.6 Returning from a Routine 62
3.7 Local Data Storage 62
3.8 Time Values 64
  f! y1 E1 t9 p8 y4 T3.9 Conclusion 65
4. BASIC OOP 67
: N+ y& f$ C4 Q4.1 Introduction 67
1 f4 Y' }' b- m3 H! Z  J. ^4.2 Think of Nouns, not Verbs 67
4.3 Your First Class 68
! m! [# v- {' s. O% `3 k) H* @4.4 Where to Define a Class 69
! K) n6 }6 \' B% v- b1 @! F1 A9 Z4.5 OOP Terminology 69
4.6 Creating New Objects 70
* w$ }* b/ v. M: {. o" N4.7 Object Deallocation 74
1 {- N, N; E" z. u) J4.8 Using Objects 76
2 K4 l4 ~5 Q( b8 n4.9 Static Variables vs. Global Variables 76
# B+ c  ^# K3 ]$ N- k4.10 Class Routines 78
. C1 t. J5 J8 q7 T' Z2 V0 F4.11 Defining Routines Outside of the Class 79
4.12 Scoping Rules 81
4.13 Using One Class Inside Another 85
4.14 Understanding Dynamic Objects 87
4.15 Copying Objects 91
0 ]1 A: u/ ]( z4.16 Public vs. Private 95
Contents ix
( c! C& ~1 k" U4.17 Straying Off Course 96
# i/ j( z1 k7 l$ \6 g, ~4.18 Building a Testbench 96
0 }) s5 H7 I. r5 R; q4.19 Conclusion 97
5. CONNECTING THE TESTBENCH AND DESIGN 99
5.1 Introduction 99
5.2 Separating the Testbench and Design 99
5.3 The Interface Construct 102
5.4 Stimulus Timing 108
' F& L/ q5 D# d$ V# v" m5.5 Interface Driving and Sampling 114
& i5 ^+ P% I5 U9 x6 w; \& E) d5.6 Connecting It All Together 121
5.7 Top-Level Scope 121
5.8 Program – Module Interactions 123
  p7 E# I" [3 o/ O5.9 SystemVerilog Assertions 124
5.10 The Four-Port ATM Router 126
5.11 Conclusion 134
6. RANDOMIZATION 135
6.1 Introduction 135
6 e( c8 r+ f$ z; X2 _" x6.2 What to Randomize 136
6.3 Randomization in SystemVerilog 138
6.4 Constraint Details 141
6.5 Solution Probabilities 149
, n3 w$ u; p% N+ ]6.6 Controlling Multiple Constraint Blocks 154
6.7 Valid Constraints 154
6.8 In-line Constraints 155
& P. I9 }! A( y( w6 k( v6.9 The pre_randomize and post_randomize Functions 156
6.10 Constraints Tips and Techniques 158
% v* G% F. w& v6 x6.11 Common Randomization Problems 164
; o# O6 M' ~4 u$ u) |6.12 Iterative and Array Constraints 165
" c1 o% N' ^! n. s: N2 q6.13 Atomic Stimulus Generation vs. Scenario Generation 172
4 C5 K$ u: P% Q8 O0 R4 j6.14 Random Control 175
: U, [/ ]0 h: q$ v: j0 I# {# ?6.15 Random Generators 177
6.16 Random Device Configuration 180
6.17 Conclusion 182
7. THREADS AND INTERPROCESS COMMUNICATION 183
7.1 Introduction 183
- g5 G5 ^5 a! |( B" s7.2 Working with Threads 184
. x* v( \6 P+ M$ W7 a* }0 k5 L7.3 Interprocess Communication 194
3 m  Z7 o) I& a9 K, V, K+ q7.4 Events 195
7.5 Semaphores 199
% m$ w7 ?9 R' n3 K8 k4 Y; C7.6 Mailboxes 201
7.7 Building a Testbench with Threads and IPC 210
x SystemVerilog for Verification
& S0 s- l/ Q: T7.8 Conclusion 214
8. ADVANCED OOP AND GUIDELINES 215
8.1 Introduction 215
8.2 Introduction to Inheritance 216
8.3 Factory Patterns 221
8 F$ ^) s8 W# I, b5 w3 T6 L. R2 c8.4 Type Casting and Virtual Methods 225
/ H: ^- N* k6 X5 T$ a9 F* q1 ]8.5 Composition, Inheritance, and Alternatives 228
( h3 E( y6 D5 V/ r2 u8.6 Copying an Object 233
8.7 Callbacks 236
8.8 Conclusion 240
/ l0 H, }# Y0 |" L9. FUNCTIONAL COVERAGE 241
9.1 Introduction 241
7 K/ Z/ b. E' F6 k- y9.2 Coverage Types 243
9.3 Functional Coverage Strategies 246
; `# X! J- S) d, Q: E9.4 Simple Functional Coverage Example 248
9.5 Anatomy of a Cover Group 251
9.6 Triggering a Cover Group 253
3 O* ?' M/ w8 S/ B( `( {. z9.7 Data Sampling 256
9.8 Cross Coverage 265
" m" M6 |6 J" V5 ^2 H3 c9.9 Coverage Options 272
" z! X5 ~. P# g+ \9.10 Parameterized Cover Groups 274
- t, G& M" b3 B  l9 \9.11 Analyzing Coverage Data 275
( I$ p) H8 v+ ?3 |2 W  o: `9.12 Measuring Coverage Statistics During Simulation 276
4 o( g+ r6 G: L) a& ?" d; U9.13 Conclusion 277
10. ADVANCED INTERFACES 279
10.1 Introduction 279
% A  r$ x) p$ ~, V2 k& c7 @+ K10.2 Virtual Interfaces with the ATM Router 279
, ^1 o; [& {3 e! M' x) g( E; m10.3 Connecting to Multiple Design Configurations 284
& n4 `: d% g5 `8 `10.4 Procedural Code in an Interface 290
8 W1 X6 b5 U0 Q% h10.5 Conclusion 294
/ j5 r) R& Z0 G( a) SReferences 295
Index 297
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