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补丁包更新列表！# m2 G/ \0 e6 U% [3 x
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DATE: 11-20-2015 HOTFIX VERSION: 061
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CCRID PRODUCT PRODUCTLEVEL2 TITLE7 s8 O: ?: ~2 W- M
===================================================================================================================================; E& Q2 q4 _+ q" F3 f# S
1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
) K# M" x+ }6 g4 b3 c1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init& V. Y8 K0 k+ o5 m d$ e3 I
1413248 concept_HDL CORE Import from another TDO project makes the block read-only1 V, t) l r* x1 y' Q
1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
1 u( d3 p" e4 e1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins; h! ^9 H% f& U# P5 s" x5 C
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
4 s" |8 {; ~# M$ S/ r4 W1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin3 U' C2 r3 h( V2 ?! i# M
1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools9 i$ W- z2 |, T: w# f+ w1 x
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename3 L& Q+ \/ _/ W- c |9 U( _- r
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets9 d+ ^: K8 o! s' {) U
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
! e6 s0 n9 }- u& |, C$ f Z1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
) ^% \1 Y7 c4 [1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable% J( Y( W/ \$ D
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets4 n3 |5 x$ Z: @5 I. L# {
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
3 e, Q7 \6 b4 B T9 X1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues: j8 T' M v, Z5 O7 {$ S; X
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
* W( ?. P/ S9 [4 B1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project* b: n8 n6 p% V; `, c
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.; [# w& T. _$ F2 }2 t R, r6 t! J1 v. X
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility/ n7 n. R5 U3 p5 f( P$ Q# ]0 K
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems1 k1 u3 S: \/ i9 M o% L" K8 `/ P
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
% i3 ?- M' J. x* k5 E2 @1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior2 A* i6 q7 H3 Z5 v5 A+ h
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board
- f2 \9 j: A( b4 S1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager5 Q! y8 `; V" ^
1490299 SCM OTHER ASA does not update revision properly
& A0 t1 F2 |0 R( T ]4 Y1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer
. j, Z6 S# z2 [; @' J1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints8 ^4 }6 |+ A% _+ z9 z7 a6 U
1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
% z7 ~, N2 a' X* u/ k1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
9 q& O( u% T% N& O1 k; n1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash
Z# v* i) S6 T" _, b+ J! r1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
# P) B6 h: h' W# g1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581( [! l/ z. U! X% |' {
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size5 `3 i9 O8 R0 \* u+ a0 ?
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root
1 Y6 r6 g8 V; K' e# x% y& S/ `1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file( Y7 ^1 n _" `9 [' @* w! [' Y5 R$ d$ q
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
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) b! Q. H8 s! d$ h- N8 Q最新破解包列表！
, J6 [+ s& W3 E5 ]------------------------------------------------------------------------------
( v' b6 {/ p4 @7 v$ _) h" g6 H& wSPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015
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CompBrowser16.60-s037wint
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1 X) ~+ S- H" ~* E, }! vDSCore16.60-s055wint, p. s. H; ~& r: c% K8 Y9 C6 K
DSSchgen16.60-s030wint
4 F2 M% @" A3 O9 c5 O# zDSSetup16.60-s010wint0 \0 \4 A. p/ d' [8 i! N1 Q9 l
DSTableEditor16.60-s018wint0 {: p2 b2 I. @* X7 i
DSTextEditor16.60-s015wint
$ f+ U. U4 P+ Z; z: O% c' w2 z# KDSUICommonIndep16.60-s0193 g) n7 i3 S, n& ~: ^% K! n
DSUICommon16.60-s026wint
/ a; I3 M% D: W o& JDSUIUtils16.60-s037wint5 P4 U' ]4 l- o8 H+ i" o3 J
SPBIX06116.60-p002wint
" d# w, x: Z$ ~0 D wadpPDFLibs16.60-s033wint
# I0 p; G8 k$ K" L1 _advanPakgDsnr16.60-s129wint
z+ ?9 Q# B n& @adwLRM16.60-s033wint; t0 S; F' H. z3 l
adwSDM16.60-s044wint' ]5 o; u8 r; Q7 E+ A% k
algroAcad16.60-s122wint: T o- X7 y; H. O' q2 F7 H# y) {' o
algroArtwork16.60-s122wint
: [% Z& ~. z' [8 ~4 UalgroAxl16.60-s048
u7 a" M. \2 f: h% palgroBase16.60-s129wint
9 g' u) {% G; L2 _1 m+ t1 TalgroCxt16.60-s077& `6 m, [* e4 g( e- b9 ~0 i; |
algroDBTools16.60-s124wint
8 E$ B: s9 e& m3 c( e) |4 N1 nalgroDsign16.60-s122wint
4 a9 ]- v" y) yalgroF2B16.60-s122wint7 P# o6 z( r% ^2 d! ^$ W' |' ]
algroIDF16.60-s122wint. h2 Y" m, G6 q* @. W* T+ U+ L9 Z
algroIgin16.60-s122wint% \8 h; z3 g( J1 X" H) _ W( a
algroIgout16.60-s122wint
5 ?/ j e8 |/ p) a1 B6 v4 y0 ZalgroIpc16.60-s122wint3 d( ^0 \& J: F* e* k6 n# ^) P
algroMfg16.60-s122wint
2 M: H( ~8 ]% \* PalgroNetin16.60-s122wint" b4 O. u- Z' u& f4 d
algroPlace16.60-s122wint4 x% k& f7 R4 N5 t7 V6 k- ^
algroSgnse16.60-s122wint
$ ]9 l8 N! b4 j& }$ E/ {& N* H5 EalgroSpif16.60-s122wint
$ V& M1 K' ~+ b5 D" JalgroStrm16.60-s122wint# T( A, j6 W- f* Z/ Y6 b6 ~
algroTextIndep16.60-s089
; C) a* b' ]% E8 S, l3 [algroTransltr16.60-s121wint7 ]/ r4 e( |, S& j+ [& e
algroUtlty16.60-s122wint, Y& B* S$ t! i8 [$ Q
bom16.60-s030wint
0 J. z3 J. O1 x' N j0 Z$ fcapPSpLibMAB16.60-s018wint
& d$ H5 [' s4 e1 K$ d; W) t$ lcapProg16.60-s044wint
0 b9 w2 F" E* B, S$ @' Qcheckplus_exp16.60-s023wint: b% H; o6 f) X, M! r
conceptNT16.60-s106wint" G* U/ q" K. [! G- S s; g/ j9 c- q
concptSetup16.60-s015wint
& ^6 t6 `7 t- v& \3 a3 C% U8 ~consMgr16.60-s104wint s1 u- m) _* @; J' J8 ?+ X
desSync16.60-s019wint# h( n) O& h: B3 O5 g2 V, E# O
eCWCore16.60-s009wint
7 J; N: D( L% O$ S; KfetBase16.60-s034wint
' ~& t$ m& v0 r8 \icpCommon16.60-s122wint
! S: I0 t& U; r* G+ }: Niff2hdl16.60-s010wint1 H0 B- j; f' h- j5 F" d
lmancore16.60-s036wint
! i" H' s6 a7 M5 nlmanext16.60-s012wint
A/ d8 `, I. ^* ^ ^, Zlman16.60-s023wint3 n5 ]( n" \: i
productServer16.60-s084wint) X/ e1 w$ t$ [" @4 O9 ^3 u" l
projMgr16.60-s015wint
2 b' v6 e9 ?' a: FpspProg16.60-s043wint
4 t% z* F @0 Yrfpcbfe16.60-s026wint6 f& z y1 j% m7 @! o8 w& q
rfsipPcellIndep16.60-s005
p7 r. W% \% a" c3 B3 PsipDsnr16.60-s128wint
+ `5 r) @5 v; p8 U& R" mspbFPGAPlanner16.60-s065wint
$ @4 G8 r+ \1 N0 ?specctraQuest16.60-s122wint
. Y1 f2 U8 b: ospgSignal16.60-s123wint
7 ]5 B/ c* t5 P c$ [6 pvedit16.60-s043wint& k7 p8 g6 G# D
4 n9 A7 v( X1 A: P4 B补丁包种子！
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cadence.spb.orcad.16.60.061.hotfix.rar
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发表于 2015-12-3 09:33
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