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补丁包更新列表！
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DATE: 11-20-2015 HOTFIX VERSION: 061
: }* g K8 m+ H. I2 }===================================================================================================================================
9 h @8 j$ O& p% W7 ]. E4 HCCRID PRODUCT PRODUCTLEVEL2 TITLE0 t+ Y* {. B% j! o7 v ^
===================================================================================================================================
3 n$ Y8 x: f5 ^3 T" U$ M1 B1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
U( @* p2 L$ Q5 c1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
6 ~! i$ G1 a" I! W$ n; {1413248 concept_HDL CORE Import from another TDO project makes the block read-only
5 ~9 N$ C/ O* p. M1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
0 f7 G( V" u% E1 h6 r$ k1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins! \9 Z5 _& B4 M( f4 \
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set+ V5 U% g7 k7 z& [
1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
" T, {8 `2 d! |. p$ P" `1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools0 }' c9 w$ S2 o5 S. w
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename$ Q! I0 s t+ b! u3 d \+ u; e: ~
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
3 ?. v2 S0 |+ M. e7 e3 ?1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
* i1 ], ~. `+ l1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
) T; s+ N" j/ _4 b1 y1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
/ |& N; ~7 R: X9 I1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets2 {: n# I1 O! I! e$ f6 B
1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice/ M# X$ z* b" a& Y$ R' B$ o1 k
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
+ Y8 c& N; ?) w/ C7 t1 d8 e1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only
6 C# Y- m; L" T) @# G) w1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project
4 G3 Z D7 k9 s N7 _2 F1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.# I) U3 z# w% F
1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
8 P9 U+ C5 ~; M1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems* R+ H1 {6 M0 |5 N/ I; \2 r
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported# _& ~4 M* h1 E9 d+ p+ O0 r/ `
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior% }6 f( Z: ]* o# e
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board( u& e; y: n% m/ Q* F1 X% M, y
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
7 c# ]0 ]2 H' c9 e5 U0 W1490299 SCM OTHER ASA does not update revision properly0 d+ ?/ T$ M9 j& C! a
1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer/ s# N& F8 [ q( {$ G+ e
1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
- p9 f* o% D/ s1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
9 R% M# j, K. n# M1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
7 Q$ T' A" r* k: c3 r1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash" O! {. h( I7 a: i& j
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
% x6 m) Z4 A- k, c4 l1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581# e, N; N& l: n9 A' x
1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size( E# I Q% g- F4 N X
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root, I/ ?/ P: ]0 [9 X9 w" j
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file# O3 K- L( ~& l5 i
1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60
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% j" D) ]) q$ h8 K \) G- C最新破解包列表！) t& s M) `/ u; S# Y+ Z& P v
------------------------------------------------------------------------------. V6 b9 u# R3 Z6 q; g
SPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-20156 u9 f4 q8 V9 Q3 w. U9 c
------------------------------------------------------------------------------
& E2 F& ?: i" Z1 F7 qCompBrowser16.60-s037wint
- d6 l4 L1 e TDSCoreUtils16.60-s077wint
( v: W' y" N" E% D- |: z$ p% NDSCore16.60-s055wint
# X) e+ @1 E5 }DSSchgen16.60-s030wint- K0 u& q; ]! c4 p2 C* _+ {
DSSetup16.60-s010wint0 B4 J+ \$ m1 H. J/ @. c( k1 a' G2 C
DSTableEditor16.60-s018wint4 ?0 E0 ~" P5 n9 @- o
DSTextEditor16.60-s015wint! M; C6 j5 D( T
DSUICommonIndep16.60-s019
" K- y) E$ P" G( S9 IDSUICommon16.60-s026wint
7 f9 ]" _5 o' b# j7 Z7 `DSUIUtils16.60-s037wint# ~, e7 l5 P) Y& z5 y+ s" E$ s
SPBIX06116.60-p002wint [3 w- e; v# D( a
adpPDFLibs16.60-s033wint* x, _& h2 n& l, T3 c
advanPakgDsnr16.60-s129wint
7 w- n3 W% q ~6 h) x" q9 E$ ^' Y0 uadwLRM16.60-s033wint4 f0 K0 z! @' e' A) Y" S3 a: }
adwSDM16.60-s044wint% K$ Q; s4 c0 b: y
algroAcad16.60-s122wint2 y/ H n+ r! J* T
algroArtwork16.60-s122wint
1 A, Q/ s/ A% Z" E" s QalgroAxl16.60-s048
: z6 Y; B, ^: ?' U( c) z2 J5 EalgroBase16.60-s129wint+ x% ]. T6 h% I8 q2 ]5 \5 J
algroCxt16.60-s077) F9 z( d' O0 X5 K+ @
algroDBTools16.60-s124wint
8 V' G8 u8 ?; h* o5 ]1 }* u; M, ealgroDsign16.60-s122wint
: N; a% X! X! ~" xalgroF2B16.60-s122wint- {" G6 J: u/ m4 g
algroIDF16.60-s122wint
$ H9 j$ B, M5 `* k7 j# u0 RalgroIgin16.60-s122wint
" h/ B! P- b8 _+ palgroIgout16.60-s122wint: l9 Y9 n4 [# |' c* Q. F
algroIpc16.60-s122wint
F1 [/ E7 h& ~, T. TalgroMfg16.60-s122wint; H8 m/ j- @- L: [. F% t
algroNetin16.60-s122wint
9 E* j, D$ g6 R" falgroPlace16.60-s122wint2 P) q$ c! j3 |; ~/ r
algroSgnse16.60-s122wint: ]! X# y* w6 c- @ ^0 O% N5 R
algroSpif16.60-s122wint/ D, V U0 o, y, k# o# K
algroStrm16.60-s122wint3 d) E% o/ v h7 u. p
algroTextIndep16.60-s089% T1 g1 I8 r) g9 j% o- r
algroTransltr16.60-s121wint
7 ^/ M6 Y f$ L' ^+ G! N% l) ]algroUtlty16.60-s122wint
7 v* E- @) o3 s# k" Xbom16.60-s030wint$ K6 W* b$ Z @' K s
capPSpLibMAB16.60-s018wint; E* P) a4 E5 m' H( M
capProg16.60-s044wint
7 J3 h2 G: g* f& Z0 Q4 echeckplus_exp16.60-s023wint/ i- Q5 R6 e d6 ]
conceptNT16.60-s106wint
+ m/ C2 w7 b: x) u0 n# k% |6 pconcptSetup16.60-s015wint3 z8 p' E, a5 I; |8 a
consMgr16.60-s104wint
: X2 H2 P1 R; S/ u7 ndesSync16.60-s019wint
8 k w( V D9 E1 o$ ]4 |eCWCore16.60-s009wint7 g- D! V- R. V9 @1 [
fetBase16.60-s034wint( R" o# h" ~3 I' M
icpCommon16.60-s122wint
. I! @5 v8 _$ S& j( v# `, M: Aiff2hdl16.60-s010wint3 B9 Y( v5 S4 z; R9 L" S3 C4 {
lmancore16.60-s036wint
7 O! O% P" a( V& Mlmanext16.60-s012wint
2 t( V+ n" L) D7 O' J/ Elman16.60-s023wint4 E% r' D5 b6 j
productServer16.60-s084wint+ X2 g' n1 a4 T2 i, X) i$ e
projMgr16.60-s015wint
- f) I7 N9 p: K6 ~( PpspProg16.60-s043wint2 h9 l( `3 b0 ]: \0 z- R
rfpcbfe16.60-s026wint
4 A+ D9 |* \8 f' Z5 ~9 z g- VrfsipPcellIndep16.60-s005
: i6 x/ ~1 ]* [8 F/ R7 t( H* UsipDsnr16.60-s128wint v0 O7 \# O6 V: e
spbFPGAPlanner16.60-s065wint) a4 `: ~1 ~/ S' U) C" N
specctraQuest16.60-s122wint
0 {6 v* f: b3 f. F; t( i% J: t" X& YspgSignal16.60-s123wint+ J/ {+ P }5 w
vedit16.60-s043wint X% o) X, ]7 {
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补丁包种子！ [& @& z% X+ I% X% F$ K
cadence.spb.orcad.16.60.061.hotfix.rar
(17.88 KB, 下载次数: 1069)
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发表于 2015-12-3 09:33
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