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6 [8 h7 ?. h* y- E5 ^0 J6 XDATE: 11-20-2015 HOTFIX VERSION: 061' {: O+ a* d0 L
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1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value
9 v) n2 c6 C9 ~9 `( _+ s1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init: P* a7 k& t5 c0 @: j ^2 P
1413248 concept_HDL CORE Import from another TDO project makes the block read-only, u/ X/ Z% h! A1 H+ \/ ^
1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle0 G& Q+ o7 x# b. S! y3 h9 l
1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins z; w h, O- r% O: j. v1 I% k7 d( J2 k
1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
4 w# E! {( P( {1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
* B# v5 {7 C# G1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools2 W0 S4 q) ]9 R- b$ j3 o
1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename! ~5 S; |+ o2 a! C- ~% C( D& r T
1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets
+ |" C1 R g4 x1 ], Z1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL" \1 J) l( Y" g) G6 l$ d2 {; S
1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy
$ K/ n H+ \9 z5 w; n9 ~+ \1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable( Y( ^! x7 Z- X- O7 Q" n W9 S
1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
1 ?; ?% c0 q B$ h' b; P1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice
, _2 {; {7 w3 n1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues) i+ a% q4 y a# }+ t- W8 k" x
1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only3 Y+ m. n4 I/ [5 ?5 T" M
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project' q% ~$ b; B C; k4 s; y+ M* M: @
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
9 u3 S9 n3 F# x8 z' c1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility& a$ c: u# s: z! e n7 g
1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems- |9 `: _/ U- h' ^. i0 Q9 v
1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported9 p3 F; |& K. }- R
1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior6 K. K7 ~4 L- }% X4 `
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board" I" _0 R) i9 q
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
: K0 C S0 R+ k9 d; v6 M1490299 SCM OTHER ASA does not update revision properly
2 m+ w' ~$ ~+ @2 ?. _0 o. f1 N1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer
, Y; Y$ f5 u j5 H) u1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
1 |$ g1 ^0 A5 c q1 u1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working" v& e# h0 Q, N1 N; ~
1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong# j1 B# {# ~0 P1 r- L# t7 z7 f
1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash8 X1 f* D) J& g+ ?
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL+ p' N9 O! X& h; c# T% {
1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
0 C; p T+ ?" g+ E1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size3 r( K: K' _# k7 x
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root9 Z% I. W3 P1 A% C/ ^' ^
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
' Y& F& e' |0 _$ A, r1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix607 ~8 L" l- W- I0 t+ {8 T$ o
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最新破解包列表！& V4 o. v4 |& b" }
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% I* z5 T. \% m+ bSPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015" h3 H$ |* u& V; A1 p% n* d
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DSCore16.60-s055wint
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DSTableEditor16.60-s018wint
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DSUICommonIndep16.60-s019 C3 T- W) a' v6 n j0 d+ z& k
DSUICommon16.60-s026wint. h. k/ {, E5 K- l" O9 E
DSUIUtils16.60-s037wint; m6 D. A6 Z; L: `
SPBIX06116.60-p002wint
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advanPakgDsnr16.60-s129wint
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adwSDM16.60-s044wint
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algroBase16.60-s129wint
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algroTransltr16.60-s121wint
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capProg16.60-s044wint
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productServer16.60-s084wint
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rfpcbfe16.60-s026wint
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spgSignal16.60-s123wint
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6 R1 z8 T" U' D* y- v补丁包种子！
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cadence.spb.orcad.16.60.061.hotfix.rar
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