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DATE: 11-20-2015 HOTFIX VERSION: 061
) e$ ^/ X# Y6 h! x3 M+ V8 i===================================================================================================================================
& ^. g8 \3 U9 O3 |9 S) |" a. \0 T& ZCCRID PRODUCT PRODUCTLEVEL2 TITLE9 I" s) X% U) ~5 h; m$ I) L
===================================================================================================================================
' a1 h, @6 Y% S1306441 APD OTHER The Minimum Shape Area option in Layer Compare uses an unspecified value9 N% @9 V) M& S, r6 g0 h
1342644 ADW COMPONENT_BROWSE Need directive or method for Component Browser to load a search criteria file upon init
5 x3 J1 P$ p2 F8 ]$ P3 Q1413248 concept_HDL CORE Import from another TDO project makes the block read-only
7 ?& z0 N9 C" }$ N5 B! X" w1417429 allegro_EDITOR INTERACTIV Pick box only accepts 1 set of values. You need to close the box and reopen it to draw a rectangle
) ]. ?% [! g) M& u7 j( a& S0 B1417442 ALLEGRO_EDITOR INTERACTIV Spin via stack and only part of the stack spins
; @( G% G) ?; ~7 T9 c4 P* n1451977 CONCEPT_HDL PDF Origin of PDF mediabox not starting at (0,0) when PDF page_height and page_width are set
1 n: [: K6 k+ {, h) c1453527 ALLEGRO_EDITOR EDIT_ETCH Contour route hugs the outer edge of the route keepin
& g/ |% ^. @# |1 w1464948 PCB_LIBRARIAN VERIFICATION The errors/warnings do not match between the various tools
. `) ~! {9 n7 B; M9 R( O! q, ]6 A1467826 CONCEPT_HDL PDF PublishPDF from Console Window creates a long PDF filename
7 w* i% N& A0 I1 J1 Y1478639 CAPTURE OTHER Capture Browse Nets window does not display all nets A; o, j( h% v
1479177 SIP_LAYOUT OTHER Pin pair constraints do not appear to be supported in Sip Layout XL
6 }+ r) R) }( M. A# O) Z* F% c( P% E1479227 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule flagging invalid voltage in hierarchy6 r, W" M5 f, R3 f$ j6 q8 j
1479454 CONCEPT_HDL OTHER DE-HDL issue: locked DIFF_PAIR property is editable
( u3 j( B7 x( [9 a0 P- T: J- v! D3 ]' S1480293 CAPTURE PROJECT_MANAGER Capture hangs when searching for all nets
- s; d6 ?, g9 C: N$ _- J1483894 CONCEPT_HDL CORE Import Design hangs when pull-down arrow is clicked twice' c5 q' a" ^* b. `
1484781 CONCEPT_HDL CORE Three different Hierarchical Viewer issues
- a% M9 B) P9 K0 U1485059 PCB_LIBRARIAN CORE Part Developer pin attributes are randomly marked as read-only1 x! x L! O; H+ k
1485960 CONCEPT_HDL CHECKPLUS Custom DE-HDL Rules Checker rule is crashing the project* [+ n, J1 k9 l# t# r6 L; Q" L) D: j( S
1486086 ALLEGRO_EDITOR ARTWORK Cannot generate artwork.
5 L4 J/ L1 Z% f1486834 CONSTRAINT_MGR OTHER Restore the Status column in cmDiffUtility
! L; I j9 ~3 z% K n: P* t8 h1487085 CONCEPT_HDL CONSTRAINT_MGR Import Physical with the Constraints only option reports problems
. G# D8 Z/ `( e1 S1487197 ALLEGRO_EDITOR DRC_CONSTR Drill to Via DRCs are not being reported
' X2 p& _7 U/ ]8 L: P7 P1487265 CONCEPT_HDL CORE Replace command in Windows mode shows incorrect behavior T9 S1 d0 Y7 I& P' E D2 i
1487733 CONSTRAINT_MGR OTHER Running Export Physical - It takes over two hours to update the PCB Editor board0 A) w: B5 S& Z2 N n
1488758 CONCEPT_HDL CONSTRAINT_MGR CM_VALIDATION_ON_SAVE should be a hard stop on Constraint Manager
- L) p# M) f' \/ S8 |& f& ^1490299 SCM OTHER ASA does not update revision properly
4 P5 L! c' g$ h, r) J5 V h [% g( U1490744 ALLEGRO_EDITOR skill axlChangeLine2Cline changes line to cline and places it on the TOP layer
) M. r, g/ a. [$ i1490924 F2B PACKAGERXL Save Design/Export Physical is resetting Via constraints
5 J8 j2 }/ o% W' `9 i' i1 r `3 ^1491351 ALLEGRO_EDITOR OTHER Create Detail for bond fingers on a custom layer not working
% |5 `9 J1 S1 f1492595 ALLEGRO_EDITOR MANUFACT Dimension character substitution help is wrong
% X* ], L, N0 Q1 R# U/ U1492777 ORBITIO ALLEGRO_SIP_IF OrbitIO import of customer mcm results in crash s' j- R) j9 l" J# [
1492901 CONCEPT_HDL CORE Cannot instantiate a multi-sections symbol (> 10 versions) in Design Entry HDL
/ R8 _: M, @* s! Y+ m9 z1495621 ALLEGRO_EDITOR INTERFACES Oval pins are placed with wrong orientation in IPC2581
1 b7 c2 W1 S% o8 O' ]$ | T1497597 ALLEGRO_EDITOR DATABASE Show Element on pin shows wrong drill size: ?2 k( c8 L. e
1497956 CONCEPT_HDL CORE ADW Library Flow test schematic generation crashes DE-HDL while saving the design when using customer adw_conf_root) p3 T" M, {3 B: J( ^; p
1498234 ALLEGRO_EDITOR ARTWORK PCB Editor fails to create artwork and no error is listed in the log file
7 k9 ]8 q6 G$ r7 O; A2 j, O1499363 CONCEPT_HDL CORE Custom attributes under variant management stopped working in Hotfix60' H- W# Q m6 @6 U0 r/ [
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最新破解包列表！! p$ z/ O; c6 m7 G$ ?
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0 |! t7 |2 V# r5 M# ^* pSPB 16.6 UPDATED KITS RELEASE: ISR 16.60.061 EST.DATE: 11-20-2015
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CompBrowser16.60-s037wint5 Y2 k* J* v& k2 k/ {
DSCoreUtils16.60-s077wint) Q' E1 S1 E5 t2 n, k Z
DSCore16.60-s055wint
: E- B' f. t+ }! ADSSchgen16.60-s030wint
% u( t% {( G2 ?6 m) V- L. X" vDSSetup16.60-s010wint
! m' ?# n' s6 Z* z, T8 iDSTableEditor16.60-s018wint
* Z7 I. a0 c2 ^) P# @DSTextEditor16.60-s015wint( U: Y! E- B( W* P
DSUICommonIndep16.60-s019
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DSUIUtils16.60-s037wint$ s9 S5 |/ ~1 k1 i( O2 H* ]
SPBIX06116.60-p002wint4 i" d% v. w* e8 N' T+ [
adpPDFLibs16.60-s033wint
4 r \, c9 @ g: [9 W3 G0 CadvanPakgDsnr16.60-s129wint
2 y$ F( o+ f$ k% {4 |adwLRM16.60-s033wint/ k3 x4 Y" e( b+ o l# ~7 ^
adwSDM16.60-s044wint
1 r" H, j1 g8 I$ L6 lalgroAcad16.60-s122wint
" i. z1 ~3 P9 H: \5 balgroArtwork16.60-s122wint1 u$ i, N/ X, H" {, J
algroAxl16.60-s048
' {$ M" r" w+ aalgroBase16.60-s129wint* ?9 G4 P2 Z2 _" l# r6 Q
algroCxt16.60-s0771 ?$ E) R$ b2 ^; T8 R% m* m/ `2 a3 F
algroDBTools16.60-s124wint
$ i' W% p. P! E( T/ xalgroDsign16.60-s122wint$ _5 k, x2 h$ ~. ]* Y& F3 y: ^
algroF2B16.60-s122wint. O' Y; s+ ]* q
algroIDF16.60-s122wint' o5 l% x7 t, e1 A* f- I; V# W
algroIgin16.60-s122wint$ x9 a& x7 u7 s
algroIgout16.60-s122wint' x& H6 w+ l6 n7 [9 ?8 Y& I
algroIpc16.60-s122wint% k! ?" J+ j4 C V' j& ]$ V
algroMfg16.60-s122wint% u! w a6 P7 _# X6 B
algroNetin16.60-s122wint
1 r8 e7 D' W; M& K; d, p+ B1 {8 falgroPlace16.60-s122wint
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algroSpif16.60-s122wint) f9 G! a6 } B+ d8 ?0 g
algroStrm16.60-s122wint
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algroTransltr16.60-s121wint, s! z: Y5 J1 s! m+ u$ b) M
algroUtlty16.60-s122wint& x+ @- w3 t4 `8 O. G$ h4 A- W% {
bom16.60-s030wint- g# }4 n8 m/ K9 L1 o6 x% x# k( E
capPSpLibMAB16.60-s018wint. I2 ]1 [) z8 N+ i) K$ F; h f
capProg16.60-s044wint# y# E) @2 n1 J4 k- Y3 j# I5 ~
checkplus_exp16.60-s023wint
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7 l0 Q! ]& l1 x& r' L& P: h) Y" g9 JconcptSetup16.60-s015wint
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desSync16.60-s019wint
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fetBase16.60-s034wint
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iff2hdl16.60-s010wint: Q0 ~6 ` L: q$ Y/ I) A& { G
lmancore16.60-s036wint% I& d+ o4 r! }/ ^2 F# @
lmanext16.60-s012wint9 d; b. o/ \) F& B+ W! t$ X
lman16.60-s023wint/ `5 r) y' q; ^0 O$ A% S
productServer16.60-s084wint
. e4 R( b) Q6 Z( BprojMgr16.60-s015wint7 u2 s& w0 t' v
pspProg16.60-s043wint
8 N# G1 R% j4 q$ ^: _# k! rrfpcbfe16.60-s026wint
$ x- n8 e4 A* ?0 d- ~rfsipPcellIndep16.60-s005 p8 U- } B7 J8 x7 b8 j4 D2 I
sipDsnr16.60-s128wint
+ B: N; z! @! b0 \& R RspbFPGAPlanner16.60-s065wint! b& V2 M& f" ]+ R6 @; A. b. g
specctraQuest16.60-s122wint2 U% {# }- o1 Z4 V+ L- R s
spgSignal16.60-s123wint
$ w Y E6 ], Uvedit16.60-s043wint
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补丁包种子！
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cadence.spb.orcad.16.60.061.hotfix.rar
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发表于 2015-12-3 09:33
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