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本帖最后由 zgyzgy 于 2015-9-28 08:23 编辑 3 |. o1 k/ H% O' d
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DATE: 09-25-2015 HOTFIX VERSION: 058
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- _7 N; ?$ r% k878770 Pspice ENCRYPTION unix2dos should not be required on encrypted model
/ o( V, H7 I g1 a# S7 H# j1450418 allegro_EDITOR PLACEMENT PCB Editor crashes while peRForming Place replicate update
! {5 P% g/ o6 h) n; @$ S8 V! s1457138 concept_HDL CONSTRAINT_MGR The devices.dml file is different between the _automodel and CM launch$ v0 O2 Q8 i# i$ S7 K* U
1462678 CONCEPT_HDL CORE Error "cannot write drawing because of errors" does not show marker window) w$ H& O9 C9 J! @1 N
1465933 F2B PACKAGERXL Illegal characters in LOCATION property are not being detected; error message is ineffective
! }( _8 E5 d* e1 u& Y- ~1466513 F2B BOM Batch utility to check if design needs packaging( l, H M# G5 U/ i% K
1466610 CONCEPT_HDL ARCHIVER Archiver should include full cpm file, not just local file
5 K2 R3 F2 |7 k2 m/ U+ t* y1467283 CONCEPT_HDL CORE Tools > Options does not warn if the .cpm file is read-only
. y- S, z8 I9 [9 ]' \& m1467287 CONCEPT_HDL CORE DEHDL should flag illegal LOCATION property characters
/ b( h5 a+ @+ o) u! l; A1467817 ALLEGRO_EDITOR SHAPE Route keepout disappears after adding connect on pad1 b' x# I' ?4 W8 D
1468454 ALLEGRO_EDITOR DRC_CONSTR DRCs appear when removing cline fillets
$ B% r; I: i+ t; L% i3 L6 q6 }1469330 CONCEPT_HDL CREFER For center justified sig_name properties, the $XR annotation is placed too far away1 \% n; M9 _0 ]0 y s+ N
1470339 SIP_LAYOUT SYMB_EDIT_APPMOD Tool crashes when the Reconnect by pin location option is used with the Refresh co-design die command
% u: p5 w6 }6 t1470524 F2B PACKAGERXL Improve the "SPI_ERROR: Failed to save project file "project.cpm". An unspecified error occurred." error message
' }- O* n% K; ^4 x( C0 m$ f1471183 CONSTRAINT_MGR CONCEPT_HDL Ability for the cmDiff Report 'single file' option to be available via the command line
( Y# f- z/ K9 f1471200 CONSTRAINT_MGR OTHER Remove the temp basecopy pstcmdb2.dat file in the physical folder after netrev completes
$ ?3 h7 }# W& e a! }1471993 CONSTRAINT_MGR CONCEPT_HDL Backannotating constraints is not processing all objects
7 z* B- d9 z l- X% G5 h; b1472046 ALLEGRO_EDITOR OTHER Gloss option Eliminate unused stacked vias not removing unused microvias from the stack% f2 N" ^3 T, d
1473056 ALLEGRO_EDITOR ARTWORK Gerber export has additional phantom data not on design
9 [7 u* \# q n3 Z0 S F3 s1474005 SIP_LAYOUT EDIT_ETCH Slide command doesn't work as expected
3 ]# E Y9 L8 }8 ?3 P1474164 APD DATABASE Using Gloss - Dielectric causes APD to crash
8 L7 g! `# x" F; [% p( H1474179 ALLEGRO_EDITOR MANUFACT NC Route command: ncroutebits_auto.txt file is not generated for a rectangular slot
" |4 w* w, y( p" f) O9 ?' b1474736 SIP_LAYOUT OTHER Cannot create bounding shape5 S! y' D' Z0 Y/ f* c( l7 A
1478070 CONCEPT_HDL PDF schematic editor crashes when selecting the pagesetup for the PDF Publisher3 W5 j2 L B7 a2 N9 X
/ V2 d1 b* q/ y. z) Q, l3 ?正在上传文件中，分享链接稍后。。。。。。! e4 q) A% G. N
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/1 
发表于 2015-9-27 22:50
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支持！
反对！
