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本帖最后由 zgyzgy 于 2015-9-13 21:16 编辑
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DATE: 09-4-2015 HOTFIX VERSION: 0572 j7 z+ d% ]$ i
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ b! f6 p4 L& Y===================================================================================================================================& H F% q# X$ M* `
1249604 PCB_LIBRARIAN LIBUTIL Libexp verify runs both con2con and hlibftb" |4 M& \: \4 e" z2 R
1417327 concept_HDL PDF Omit mechanical page while printing PDF/ o; l4 f+ V$ Q/ |% x+ i
1440484 CONSTRAINT_MGR CONCEPT_HDL existing pcb diff pair name is changed by netrev+ d! [% e2 F# R, g' A$ `2 e
1441086 PCB_LIBRARIAN OTHER Cannot delete pin & added pins change after save/ j3 C, P) J! X! S+ \
1448066 SIP_LAYOUT TECHFILE Using a script to export technology file from Constraint Manager crashes SIP_LAYOUT! i8 r) V& H0 _- Y5 Z, E( c: }
1452431 CONCEPT_HDL CORE Obsolete $PNN is remained in a dcf file and Attributes dialog
: B: p- S, u. G) D% S1452640 allegro_EDITOR OTHER Updating PCB Board file concern
6 {: b3 M. U0 x [* I: q1454730 CONCEPT_HDL CORE Zoom/Pan Disrupts move and copy! d. e4 P A$ c0 [9 C' X5 _- ]3 Q
1457713 ASI_SI GUI Setting Sigrity_EDA_DIR for Sigrity 2015 /orcad ERC" }* q; e5 ?" G
1458439 F2B PACKAGERXL The Packager pstprop.dat file reports false conflicts in net properties9 u2 l! ?1 Z/ g. `5 H( A
1458461 F2B PACKAGERXL The pstprop.date file "Conflicts on Net Synonyms" are NOT reported as errors. B/ o/ E0 }% a( o: M# S$ k
1459153 SIP_LAYOUT OTHER Mirrored components with pads on diestack layers (above top/below bottom) display on right layer but aren't selectable.( a4 U2 x( J, k1 u* P; r' ^
1461553 CONCEPT_HDL EDIF300 edif300ui writer crashes on ADW design
& ~, }9 u/ g, r( j& I' q: }$ I1462254 ASI_SI SPDIF Ball properties are not translated to XtractIM using SPDIF6 h' c7 u- r) ]" r7 m) D0 f* C
1462441 CONCEPT_HDL OTHER Pin text alignment and overlap with symbol boundary issues on symbol rotate4 c1 w J+ g* {
1463333 ALLEGRO_EDITOR INTERFACES PDF created using Export > PDF shold not zoom to Page fit when selecting another layer
3 w1 \$ r b$ z% ~5 c1463358 ALLEGRO_EDITOR INTERFACES Color assigned to pin not passed to PDF1 Z& c7 r, e( g% D' t" f
1463648 CONCEPT_HDL CORE Need ability to block the uprev of a design
' {) ~5 ]# F$ B r9 e1463839 APD OTHER Changing DIE property to another layer does not change its masking layer
. B& d& k" a, E1464380 APD OTHER Why pad at wrong layer when we place SIP 16.6 but 16.5 is correct.
* I0 J% C* X% i v% e4 y2 t1464660 CONCEPT_HDL CORE Problems with "save hiarachy"
; e; d7 z' \& I" e2 W1464771 SIG_INTEGRITY OTHER PCB SI crashes when extracting differential pair topology from Constraint Manager& R/ n% _: u. e6 A; Q# y% c
1464909 APD WIREBOND Bondfinger drifting off of the WB guideline
% p" v# D/ g/ u( p7 m1465273 SIP_LAYOUT STREAM_IF Streamout with mirror makes die symbols not located at where they should be in gds5 r: o# N; q$ o# q" [0 n. L# R, r
1465457 CONSTRAINT_MGR CONCEPT_HDL Layer characteristics from a lower-level block are merged with the higher-level
" d p! d9 w3 Y V% e9 {1465541 CONCEPT_HDL CORE CM_VALIDATION_ON_SAVE is crashing DEHDL on startup; _& q3 \0 v# N, o1 J* U: P9 k7 m
1465543 F2B PACKAGERXL USE_PACKAGED_NAMES is crashing Export Physical
6 t3 {9 t x8 C: r' M1465911 CONCEPT_HDL OTHER Question about checks made in HDL while creating BOM
+ ]: q3 ` q1 G$ P x4 m6 h1465916 F2B DESIGNVARI Issues with variant management in ISR 055 #1 - Must save variant in Variant Editor to add info to CPM+ Q8 x0 l" I( P2 ?& ^8 X7 m4 _0 I
1466230 CONSTRAINT_MGR UI_FORMS The Clear option is missing from the Reference Electrical CSet field in all workbooks) |; v/ C c' W/ b' W- E
1466404 CONSTRAINT_MGR ECS_APPLY ECSet mapping using tags not working" k, |8 w5 j4 Z) T% ?/ J
1466492 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using the Add Connect command
& `- F% I6 T. z1467156 F2B DESIGNVARI Out of sync endless loop* N. f! @' Y+ p
1469062 ALLEGRO_EDITOR EDIT_ETCH Crash while performing neck mode for Diffpair
( T6 {+ k$ {6 i1 W( G5 x& d1469081 ALLEGRO_EDITOR ARTWORK Short in Gerber Data due to wrong cut out around via/ k* g% B) T" Z9 E
1469713 TDA CORE Updating project with non-existing variant crashes TDO- E# O+ K3 Q0 e
) @3 }! e# A& t; ]1 H1 b0 t正在上传文件中,分享链接稍后。。。。。。
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