数模混合仿真问题，求大神帮忙~~~

jmchf

我在做数模混合仿真的时候，在config中调用模拟电路和数字模块的symble，但是在进行display partition>all active时，系统报错：
\o *SYSERR: Unable to hdbBind for inst I15 in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
% h* L) F/ h( U* V: Z\o *USRERR: Selected context view string 'spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl'
\o offers no suitable view for inst I15 referencing placed master design.add_and_mult.symbol
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
\o Please check HDB configuration or library setup.
\o *USRERR: Selected context view string 'functional'
+ n1 B7 e4 C. V: U2 v8 s; f# ?\o offers no suitable view for inst I14 referencing placed master design.average.symbol
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
\o Please check HDB configuration or library setup.
5 \: Z/ y) I7 ^6 H2 m1 v# O\o *USRERR: Selected context view string 'functional'
/ ]- ^- Q$ n" P( N5 {) z# O\o offers no suitable view for inst I12 referencing placed master design.unit2.symbol
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
1 N$ |- R; F% n, w0 }1 L9 |\o Please check HDB configuration or library setup.
0 P( @, s, y3 G, f\o *USRERR: Selected context view string 'functional'
& `8 P8 g- P- d" o- S5 k\o offers no suitable view for inst I11 referencing placed master design.unit1.symbol
3 h0 L) D3 x6 j+ q- I: G8 f* {' g\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
; q4 _# Q% f* \. W$ g6 b+ E\o Please check HDB configuration or library setup.
\o *USRERR: Selected context view string 'functional'
\o offers no suitable view for inst I4 referencing placed master design.encode.symbol
\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
\o Please check HDB configuration or library setup.
\o *USRERR: Selected context view string 'functional'
# f1 D+ {% B0 J1 c\o offers no suitable view for inst I2 referencing placed master design.encode.symbol
$ o- Y- T0 t9 C  @6 A\o in cell Module tiadc, lib design, view schematic, configViewString spectre spice verilog verilogams behavioral functional schematic veriloga vhdl vhdlams hdl system verilogNetlist cmos.sch cmos_sch ahdl.
, L, g6 X! ]4 x% V9 Y6 [2 L\o Please check HDB configuration or library setup.
\e *Error* Failed to partition the design.
\e
\e *Error* mspDisplayPartition: Failed to create network
9 z, _* [/ l% `* o
这是什么问题啊？求大神帮忙解决一下，鄙人不甚感激！！！

jmchf

还有就是里面的xxxx.symble全是数字模块的，模拟模块没有出现问题