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本帖最后由 zgyzgy 于 2015-9-1 14:13 编辑 . |3 P; P2 ~$ t% }
, ]' `$ k; [0 p0 [4 b3 KDATE: 08-28-2015 HOTFIX VERSION: 056
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5 ~! h+ z' k% q" [) F( \% o1134412 allegro_EDITOR PLACEMENT Place replicate creates redundant vias and shapes- option required to prevent that
" P7 p* l- A+ ~4 V1431136 ALLEGRO_EDITOR OTHER Cannot z-copy board outline with Contract) F: i: R. c0 D
1432392 ORBITIO INTERFACES SiP db import is 鈥渃rashing鈥� if no xda inside: O. h0 z0 E- ?/ O7 Z, r2 {
1444820 CONSTRAINT_MGR concept_HDL Exporting TCF file from Constraint Manager does not output physical and spacing constraints
3 ]8 T0 h4 b) [$ ]$ p. E1447986 F2B DESIGNVARI All the DNI parts not available after saving the variant file) Z* A& s) ]2 _% `4 G4 v. \" R
1455901 CONCEPT_HDL CORE Need the ability for the front end tool license to have the High Speed option selected by default8 z8 u0 Z5 Y; i
1456280 ALLEGRO_EDITOR DRC_CONSTR DRC not shown even when the constraint is violated
1 J: y4 m8 H5 ^1458272 SIP_LAYOUT ASSY_RULE_CHECK File size increases by factor 4 after ADRC check on a specific customer design
6 {+ o' s% P, L1458960 CONCEPT_HDL OTHER Getting packaging error when SEC_TYPE and PACK_TYPE properties go out of sync due to a manual name change in chips.prt
1 L2 y+ \5 _* E1459961 CONCEPT_HDL PDF Publish PDF command issues: Logo (.gif file) not rotated, font changed in the published file
( W& D* B7 D6 G2 \9 g s1460178 ALLEGRO_EDITOR INTERFACE_DESIGN PCB Editor crashes on deleting vias or nets$ |5 X6 V" Z8 R; Y8 O$ K
1460204 SIP_LAYOUT IMPORT_DATA BGA Text In wizard ignores the primary pad layer set in text file
3 b! m5 G7 L4 S6 A2 D/ h4 o1460246 APD OTHER axlDeleteObject() command is not removing the die from the design6 q0 X+ [* u4 }& d$ ]3 C8 m; ^! l
1461387 SIP_LAYOUT skill axlDBRefreshID(nil) removes ID from assigned variable
4 B4 }$ o8 z2 l6 d1461625 SIP_LAYOUT ASSY_RULE_CHECK Core polygon routines are not creating proper polygons; ADRCs reported: "acute angle", "exposed metal to exposed metal". a0 D* Y" K' b1 r3 r
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