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DATE: 07-31-2015 HOTFIX VERSION: 054
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CCRID PRODUCT PRODUCTLEVEL2 TITLE, q u3 a: P9 q- x# }+ _
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694479 concept_HDL OTHER Need version control of symbols in DE-HDL0 q, V% g5 K- r! `/ H4 ^) ~
695025 CONCEPT_HDL OTHER Version option of Add Component should filter mismatched versions7 G. Q+ m" R6 d+ C
1004049 CONCEPT_HDL OTHER Grouping of PACK_TYPE specific symbols by version in Version and Version List' u$ R3 F# l0 x7 h7 ^
1357843 allegro_EDITOR PLACEMENT The net association of a via changes when a replicated circuit is placed using Place Replicate; y* K; h* g' B; x
1367917 CONCEPT_HDL CORE The PIN_TEXT property of a symbol increases in size when rotated at 90, 180, or 270 degrees `& j1 B% S: x$ ]! a+ Y6 x
1405364 ALLEGRO_EDITOR EDIT_ETCH Slide Via snaps to the near by vias
# o) a F, y ?, x1412635 APD DATABASE APD crashes on saving design3 y# x% y0 D' | O; ~
1413214 FSP FPGA_SUPPORT Need spreadsheet rules to support FPGA devices
1 I- K. e# i$ e/ {0 w0 l Q* w1427732 SIG_INTEGRITY SIGNOISE Constraint Manager does not display results of Xtalk simulation
Y# C! w2 O W1 {7 h( A; _0 U1430416 ORBITIO OTHER Importing a .sip database to OrbitIO should also import the shapes.
4 S2 V. t5 Y6 \$ Z! F5 s1435246 ALLEGRO_EDITOR SHAPE Shape shorts with signal net in artwork in SPB166 Hotfix 50
& v. f! L- F9 f: w* f% |* c7 d1437479 CONCEPT_HDL PDF The Publish PDF form appears truncated when the screen display is set to "Medium - 125%"
$ r" Q8 N5 ]+ ~+ x2 Q* x1438848 APD OTHER Layers of a module, mirrored using the Mirror Geometry command, change on refreshing the module
2 F0 ?' k* ?7 e8 {! H1439536 SCM IMPORTS On running Import Physical on a .sip file with a die abstract, wrong pin names are generated) C' m% e8 c" _1 _7 M2 L% ~
1440332 ALLEGRO_EDITOR ARTWORK The oblong slot hole changes size in the IPC2581 output; [/ b P. A+ a
1441408 PCB_LIBRARIAN VERIFICATION About Release command could not read NC_PINS property in Part Classification. j- t9 G8 L% v$ H3 I
1443224 CONCEPT_HDL CORE Rotated Text appears bigger in size compared to the normal text.
$ }( l( G3 Y% w7 f; k U1444562 CONCEPT_HDL CORE Use of Synonym not shorting nets
3 g1 o: @9 I: ^1444932 ALLEGRO_EDITOR INTERFACES When exported to PDF, the octagonal pads in a padstack are larger than their size in Allegro PCB Editor
, N7 m1 i3 f& o P) k8 W1445606 CONCEPT_HDL CORE Make the Component Revision Manager UI similar to LRM in ADW Flow
' a9 t* N ]* m1445925 ORBITIO ALLEGRO_SIP_IF Merge Update of a SiP File failed
( P6 f8 l, L) z2 ]7 ~1446259 ALLEGRO_EDITOR INTERFACES Export PDF prints a big square box instead of a frectangle on the board
! M, j: I n/ ?! V7 L( e) K$ V1446792 CONCEPT_HDL CORE BOM-HDL: How to output attributes attached to the instances of reuse blocks
8 z# I/ O, S L, j3 A1446866 ALLEGRO_EDITOR REPORTS IMPEDANCE_RULE values not being extracted in reports9 O3 D7 X/ e# m1 R! j
1447863 FSP MODEL_EDITOR Ability to assign clock pin to QBC: {% C2 ~2 P) |' G
1448802 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes on routing across constraint region boundary
1 [6 M! X4 G# w4 L& x1449255 ALLEGRO_EDITOR OTHER Edit > Change causes Allegro PCB Editor to crash.4 r, E! V! h8 \
1450470 ALLEGRO_EDITOR EDIT_ETCH Return path vias: need provision to specify spacing value of less than 1/ x) T2 ~1 a6 l7 P2 z
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发表于 2015-8-3 11:54
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