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本帖最后由 zgyzgy 于 2015-6-29 19:30 编辑
# @5 v1 _8 s/ M. E6 D: a' k0 [ X% v5 y
这次出大招了更新好多。官网显示是52，DATE里面介绍是51：/ d3 A% a: A* i0 s( l
DATE: 06-26-2015 HOTFIX VERSION: 051
* ^ A7 X, S2 W2 t5 ^===================================================================================================================================$ M- `+ s4 q3 b+ s2 {
CCRID PRODUCT PRODUCTLEVEL2 TITLE
- T- _2 m+ H* t6 [" K1 i===================================================================================================================================7 P2 d& \/ E1 \4 } @5 q
295747 allegro_EDITOR PLACEMENT Place manual form takes a long time to open' m( Q5 P6 F3 Y: C( H
713130 CAPTURE GENERAL Bias points get displaced when schematic is copied/pasted in MS Word
% {) e7 `. w% y* @/ O832170 SIG_INTEGRITY SIMULATION IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
( \- z+ i3 E# W9 [/ B, M+ L, F926138 SIG_INTEGRITY SIMULATION IBIS buffer results with two TV curves do not correlate with HyperLnx or MATLAB results
4 m- f. F- N& t5 l, G6 g1056824 ALLEGRO_EDITOR INTERACTIV Need a way to repeat the 'Snap pick to' selection V$ _1 C6 x9 {* i
1131613 concept_HDL COMP_BROWSER DE-HDL: inconsistent display of hyperlinks in Component Browser& \4 r4 V3 z" H% `0 A o
1156766 ALLEGRO_EDITOR INTERACTIV Retain selected options (lasso, polygon, or path)7 X0 C, H x7 p; t3 S2 T/ L) p/ {
1224882 CONCEPT_HDL CORE Unable to modify the port position on the sym view if the signal names have double underscores
$ C) V8 e7 ?+ n4 ?' @/ o- y0 T1225998 CAPTURE NETGROUPS Bug: Normal scalar hierarchical pin is getting changed to netgroup pin! R( x. k1 R7 e! y7 B6 e+ j& C
1281668 ALLEGRO_EDITOR EDIT_ETCH Arc bump of AiPT; I$ X$ h% n$ Q; p, S+ O2 b
1286749 FSP PROCESS FSP not allowing group swap across inteRFaces in same_vccaux_io region
$ v& m# p- O% Y; k/ _) G* w, g1306988 SIG_INTEGRITY SIMULATION Support needed for the multiple VI and VT waveforms for the buffer with TLSIM' i( ]+ Y1 R3 }& U+ C7 I
1311177 CONCEPT_HDL CORE Save Hierarchy for read-only blocks should not produce ERROR(SPCOCN-2123)
4 C# \6 Q3 C. V& s$ ^8 H( I1315888 SIP_LAYOUT ASSY_RULE_CHECK "Dummy" DRC violations with xhatched shapes filled with "crosshatch void fill" function
3 i& O4 [4 m: B. v+ U1319663 PCB_LIBRARIAN VERIFICATION con2con always reports the first part name when problems are reported for 2nd or 3rd part name from same primitive( P" C5 Z# y1 a+ _0 i- P
1321192 APD VIA_STRUCTURE When atttempting to delete a layer we get the warning messages stating its a symbol when its a Via Structure issue.
/ D2 F* U9 ]# i6 Q6 f1324280 ALLEGRO_EDITOR COLOR Layer Priority for user-defined Ref Des Layers- s+ a1 |/ F0 K: n5 z, Q
1327949 CONCEPT_HDL CORE not able to add placeholder for VOLTAGE to bodies6 c' v2 q. p2 y
1332123 APD INTERACTIVE Snap to pin is snapping to via.: w5 q. h8 y1 W; q# z
1333113 F2B PACKAGERXL A hard LOCATION
2 j' s8 e7 V I0 ?4 @8 M! B1335908 CIS RELATIONAL_DB Relational data fields order do not appear correctly in CIS BOM.7 \8 C" B3 E K# C3 X; W
1336970 ADW LRM Replaced by report does not show the replacement part/ o5 o- P6 W) W, P$ J
1337197 ADW LRM DE-HDL crashes and corrupts design during LRM update6 K% Z, x5 H& j
1337548 CONCEPT_HDL COMP_BROWSER Component Browser in the cached mode crashes when doing a search/ ^5 ]1 ?, Y6 B5 w
1341177 ALLEGRO_EDITOR PLACEMENT Need the ability to resize the Place Replicate Unmatched Component Interface window7 v/ v3 ]. ?/ y9 s8 z* z0 l
1341940 APD OTHER WIRE_COUNT check doesn't work for diepad to diepad bond1 r' y, W/ ?: b7 v, |
1341947 SIG_EXPLORER OTHER Sigxplorer hangs when the Wizard_Template_Path variable is set
# X" u9 A' v/ t1343981 SIP_LAYOUT MANUFACTURING add an option (Refdes) for Display Pin Text
' m7 T$ Z' L8 f+ m/ |2 h1345577 TDA CORE TDO crashes when attempting to check-out block
. M4 S F% L, Y" B/ M5 z1345601 TDA CORE Error message when attempting to change to ECO mode
5 n: y/ k( f3 T: f5 D4 v1345629 ADW LRM LRM deletes worklib contents when updating schematic design5 M8 A, T0 |8 ^" a1 o% z
1346088 ADW DSN_MIGRATION Parts missing in part_table.ptf after design migration
( \9 Y% q$ X8 R* r: u1346925 APD STREAM_IF Need ability to have same class/subclass mapped to more than one stream layer
. f6 `0 ]6 v. Z7 M& C3 T1347102 CIS GEN_BOM MDB file is shown wrong variant name# O% [% Y9 k7 u2 \$ ~2 k: e" O
1347145 CAPTURE INTERFACES Capture crash while editing comapre test bench settings for Pspice design6 d4 }" c. ^9 {! p" d4 r
1348619 ADW LRM LRM does not update symbol and its attributes in the schematic
: p2 t& B0 Y1 x7 B& W1351123 CONCEPT_HDL CORE Changing Net Name in Attribute or using Text > Change deletes constraints
% V& |. X! Y- C8 p l1351700 ADW LRM LRM Crashes while loading design
: J$ W3 c) V/ ]1353844 ALLEGRO_EDITOR SHAPE When creating a copper shape on the M2 layer a void is created running top to the bottom.
" U3 _" t& C9 x2 A Y8 V7 @: [1354049 SIP_LAYOUT ASSY_RULE_CHECK Exclude fillet shapes from the Continuous Solder Mask Coverage ADRC check/ m$ B7 _, q. X0 T
1354790 CONCEPT_HDL COMP_BROWSER Remove limit of 2500 for Component Browser search results
6 R3 r& i! b) |' d( H1355258 ALLEGRO_EDITOR DATABASE Matched Groups generating wrong pin pairs1 f& O" A9 h! j: T/ r
1355882 ADW TDA ERROR(SPDWSD-58): Unable to copy file ... to folder ... /.sdm/tarballs
: |9 |! }4 x1 S1357624 CONCEPT_HDL CORE DEHDL fails to recognize PTF header changes resolved by LRM4 B* \" @7 P: r; y
1357760 CONCEPT_HDL OTHER What arguments to use when starting DE-HDL with options?
. H5 E& o& ~5 @1358018 CONCEPT_HDL CORE PinPosition from template.tsg located at $CDS_SITE is not honoured for split hier block symbol generation
# G9 ]1 @: X' |" g1358053 TDA CORE TDO and VarEdit: Check out variant_cbc.dat separately
# \* j* A3 K! h5 u" a4 r1358511 ALLEGRO_EDITOR INTERACTIV Replace padstack error message unclear) P* F% J7 I+ y/ m7 x
1359168 CAPTURE TCL_INTERFACE Bug: CIS "Place database part check" tcl command not working/ z& ~- P; e1 }- P
1359357 CONCEPT_HDL OTHER HF039 BOM_IGNORE for complex hierarchy is not working normally7 a6 }9 u" {! r5 P$ f' {6 _. f! |
1360071 CONCEPT_HDL CORE The Change Properties dialog does not show a cursor when selecting
$ B$ N+ |) R" `, h6 z1360554 ALLEGRO_EDITOR DRC_CONSTR Same net DRC disappeared after update DRC.
6 _8 a+ m4 ~* a( P, p1360653 CONCEPT_HDL CORE CUSTOM_TXT_CDS not working for defprop in template.tsg
" R- e' O& Z8 Z, H8 u; ?1360772 SIP_LAYOUT INTERACTIVE Cannot change Clines to a different layer.
C2 }1 [; g' P l( v1361281 ALLEGRO_EDITOR INTERACTIV Unlike stacked vias, moving non-stacked vias requires an additional step of choosing a pick point
* d* o5 c$ O0 i6 C. U1362156 ALLEGRO_EDITOR PCAD_IN PCAD import to PCB Editor fails with message "ERROR: netname not NULL for non-etch class"
8 e4 l6 b# A+ B i3 U+ ?0 M1363298 ADW PCBCACHE Part Manager Error when replacing a part with a
1 E6 Q7 W6 q( g$ ?" V, K1365794 ALLEGRO_EDITOR PCAD_IN PCAD to Allegro translation does not generate the translated board file and also does not give any error message.7 R. l0 ? k) B2 Y( y
1366525 ALLEGRO_EDITOR INTERACTIV The "replace via structure" command of APD and SiP is also required in Allegro PCB Editor/ l$ v- ?& `/ u
1366976 APD EDIT_ETCH Interactive edit etch slide command not working as expected.
& U6 E" t" a6 o1367224 ALLEGRO_EDITOR INTERACTIV merge 'shape edit mode' into 16.69.
; E# e- ]7 R; N/ P. F3 m1367314 CONCEPT_HDL OTHER Setting lock of Reference schematic.
: h- x" T8 Z$ {" D* \. L6 t/ V# c1367609 F2B DESIGNVARI Variant overlay shows the ALT_SYMBOLS attribute for modified inductors2 v% \; `9 N& n4 o9 D/ X8 z) ^
1368091 ALLEGRO_EDITOR INTERACTIV A filled rectangle should be treated as a shape to use the "snap pick to" function with the "Shape Center" option
3 V- E3 B4 |( ^3 M1 W1368159 CONCEPT_HDL CONSTRAINT_MGR Make CM_DEFAULT_PRECISION a site.cpm directive- C" `6 V1 x# g0 P
1370186 SIP_LAYOUT EDIT_ETCH Cannot add a via to the selected layer' h: R- t$ h! A1 X$ y4 f( C
1371015 CAPTURE OTHER Tools > Update properties displays Error (ORCAP-1579); I5 F# n/ s3 q) U
1371807 CAPTURE SCHEMATIC_EDITOR Button Status for 'drag connected objects' hard to see
0 g. F& n0 \( R8 r# }& O* w8 R1372282 TDA CORE Integrator utility to refresh policy: q( [$ r( w7 |; |" X) J H9 i
1372351 CAPTURE DRC Browse DRC marker and search of DRC marker are giving different results., n9 f+ t; K: n: z" p* d
1373118 CONCEPT_HDL CORE Only generate $HOME/cdssetup/concept files when changes are made" {7 u0 R2 Z) S. |
1373412 ALLEGRO_EDITOR GRAPHICS SigXP Print Canvas: Via model is filled by a black via box R; {6 _& p! ]! P! y M( R
1373575 CONCEPT_HDL INTERFACE_DESIGN Net Group name clash Pin Name$ f) ?, A6 \$ q" h
1374703 ALLEGRO_EDITOR SHAPE Inconsistent behavior on shape voiding$ ^1 g2 w3 x2 c
1375127 ALLEGRO_EDITOR INTERACTIV The errset skill command with axlSpreadsheetRead crashes the tool
8 E$ i' ^) `; F1 s1375940 PCB_LIBRARIAN PTF_EDITOR PTF Editor error messages are truncated.
! b1 V2 a+ K2 D1375974 ASI_SI GUI want to use SigWave on SI Base
% ?: Z' c( ^4 q% o9 {1376591 ALLEGRO_EDITOR COLOR Dehighlight command with "Dehighlight All" option does not remove the color marker swatches from Constraint Manager1 ]( D/ n( |8 a9 C
1376634 ALLEGRO_EDITOR INTERACTIV Snap pick to symbol center not working in symbol editor# q. z' T5 j* k
1376765 CONSTRAINT_MGR ANALYSIS Setup/Hold spreadsheet lists only one pin pair
+ Q% Y+ g& ]2 D' y+ Z7 }, J1376851 CONSTRAINT_MGR UI_FORMS CM workbooks change after simulating- w( c. x, p. G
1377555 ALLEGRO_EDITOR DRC_CONSTR The "Line to SMD Pin Same Net Spacing" DRC appears and disappears each time Force Update is run for Dynamic Shapes
, m( k0 E4 k* ]/ k0 {1377606 APD REPORTS APD16.6 Missing Fillets Report ?
X( X/ l/ f5 Q$ i* }8 m1378094 CAPTURE EE_INTERSHEET_RE intersheet References are wrong
0 Z' S5 d5 N' `1378625 ALLEGRO_EDITOR FSP_PINSWAP FSP crashes while synchronizing design8 f4 k5 e$ M) l& h
1378703 CAPTURE DRC different DRC results even design and options not changed
2 l* w# H2 u& d: C8 c1382541 PCB_LIBRARIAN CORE Show Pin Numbers in Global Rename Pin dialog for better understanding
8 L9 e3 e8 a- z: x$ n9 X; Z& v1394552 CONCEPT_HDL OTHER The link function enhancement.
3 {! j& |& w7 A O- u1395007 CONCEPT_HDL INTERFACE_DESIGN Issue with NET_SPACING_TYPE and NET_PHYSICAL_TYPE properties depending on visibility
; Y# G1 z5 \* b4 L( i2 T6 Q# a1395033 CAPTURE HELP Project opens as text file if the directory or project or project name has .v in it.
1 v; ]1 d% X: A; z4 k9 `. f1395356 SIP_LAYOUT SHAPE When merging shapes, a certain void in one of the shapes changes location and is resized
% |5 y: V) x; k! o, ^0 A" b1397564 CONCEPT_HDL CORE Design Entry HDL crashes when opening from Part Developer0 ]' f( L R& }2 ^- G( q A
1398919 CONCEPT_HDL INTERFACE_DESIGN NG buss error
( Z0 J3 b' O; ~% C1399924 CAPTURE OTHER Error message location always shows in inches" f0 f0 ^$ ?8 ]/ ?9 q
1400086 CONCEPT_HDL CORE Option to retain the distance between Pin number and wire/pin while moving a pin number.: F" l0 y7 r4 L: o
1400691 CONCEPT_HDL INTERFACE_DESIGN Rename of netgroups is a must2 S5 W, F( l7 f2 K
1400755 ALLEGRO_EDITOR SHAPE Updating shapes on design causes a short to a pad( f' R6 s& O' f4 t/ m
1401320 ADW COMPONENT_BROWSE Issues with filtering in Component Browser
) A7 o# x; Z3 |) c& _1 [: y1401900 ALLEGRO_EDITOR MANUFACT Drill chart resized from V16.5 to V16.6% r& v" q9 d* ?5 B+ k. t. J
1402317 ADW DSN_MIGRATION Design Migration hangs in the final stage "saving the design"6 X6 n* u1 z$ t/ M2 Y
1403716 SIP_LAYOUT SYMB_EDIT_APPMOD SiP layout - Dynamic ability to applying expansion/compression of symbol using app mode
9 ^! `4 t# C# Q3 Z$ a1 l) H1404071 SCM ERROR_WINDOW About Violations window messages and Export Physical4 E5 P- Y9 ]7 ~( g1 |" l, y; @
1404754 TDA CORE setPermissions client API needs to be changed to pass only changed permissions
! a; b* D1 i; Q: J: }2 s! o1404993 ALLEGRO_EDITOR DATABASE dbdoctor falsely reports Illegal rectangle size error has been fixed.
t4 V) W, D4 F1 ?+ h1405018 ADW COMPONENT_BROWSE Need a way to move the Attributes tab first, but make the Properties tab open by default
' W Z8 m# l- F [: }1405201 CONCEPT_HDL INTERFACE_DESIGN Provide mechanism to sort the Net Groups created in the Interface Browser. O: p7 o# Y0 L9 c! M
1405896 CIS PLACE_DATABASE_P If FPLIST field is set to transfer to design in DBC, Capture CIS crashes$ r0 U7 c* x2 O, \ ?4 X
1406554 CONCEPT_HDL INTERFACE_DESIGN When trying to map a port group all members cant be selected. i. y9 {/ I; E0 J
1406780 CONSTRAINT_MGR OTHER Deleting cline segments when Constraint Manager is open on net properties bundle crashes PCB Editor, G5 N' l. f; J0 m2 k4 y- z
1407817 CONCEPT_HDL INTERFACE_DESIGN Port group mapping issues on saving design when using non-high speed license @6 Q9 z3 i! x+ ^1 Y
1408001 ADW COMPONENT_BROWSE Searchable only properties are missing from a shopping list in UCB
9 L5 b u% ?2 v, I1408414 ALLEGRO_EDITOR DRC_CONSTR Waived DRC does not move with the elements it is associated- B5 k( ~1 h" h2 w$ t$ q, W* F# Y
1409474 CONCEPT_HDL GLOBALCHANGE Global Replace does not retain refdes values6 ^# S0 @ |" L5 ]$ Z( e
1410333 CONSTRAINT_MGR DATABASE Unrouted net length does not match total Manhattan length
A0 f+ C+ H$ j9 t+ K! p1410857 ALLEGRO_EDITOR DRC_CONSTR Diff Pair Uncoupled length DRC gives different results in SPB16.3, SPB16.5, and SPB16.6.
6 b6 g+ H1 o& i( y" ]1 F1411936 CONCEPT_HDL CORE Font support for $PN is inconsistent5 s Z1 _' a3 Z$ I. s
1412878 ADW COMPONENT_BROWSE Shopping cart tooltip for PPL error has a bad character) D2 w2 v2 X8 N
1413243 F2B PACKAGERXL Backannotation warnings about $PN not deleted from Property file (dcf)2 J+ J! K1 C4 |2 a8 w, B* N8 c
1413699 F2B DESIGNVARI Provide an option to create variant-specific schematics without any variant specific color overwrites
1 ^: C8 `) f4 v5 R& M4 ~+ g1414672 ALLEGRO_EDITOR PAD_EDITOR Padstack designer Lock mechanisim fails to lock padstack when it's reopened.2 g" B' _* A. }( T- _$ F+ g, }$ t
1415863 CONSTRAINT_MGR OTHER DCF import ignores Voltage property values
# v9 z. Q5 {! c! K$ `$ o" D; |4 l1416561 F2B DESIGNVARI When using the Replace Component command in DE-HDL, Component Browser takes a long time to load
) [" g' y& t8 p: U1416704 ALLEGRO_EDITOR EDIT_ETCH AiDT Turning Pattern Corner type option to Arc. [- r- A' J) e1 g' d0 ?* q
1417283 CONCEPT_HDL INTERFACE_DESIGN Provide an option to flatten a block when adding it from Component Browser
/ @- q' j- [6 X: q1417802 CONCEPT_HDL CORE Multiple ghost images while copying group or objects
7 m+ Y9 ~) z4 {# m1 Q1418134 CONCEPT_HDL CORE Some objects are removed from the group on using the group move command in Linux! d5 ^/ ?' `4 { J
1418484 SIG_INTEGRITY SIMULATION Estimated Xtalk and Simulated Xtalk results do not match in 16.6 ISR044
0 e, U* {9 s- |5 V1419474 CONCEPT_HDL CORE CheckPlus, PDF Publisher, should detect invalid view files! B3 }) K' L* o) e8 P
1419560 ADW COMPONENT_BROWSE Removing a value from the search criteria, removes the field from the displayed results
, s, V- i3 _* e$ V3 }9 ]: l+ v% a1419954 SIP_LAYOUT DIE_ABSTRACT_IF add abstract show ic details to the place codesign die abstract form
/ h" J, b: a C+ P9 u/ ^1420459 CAPTURE STABILITY Capture crashes when library has pages with parts where pin names or numbers have been moved3 Z- b7 _2 z, w+ H F/ L
1420482 ADW LRM LRM deleting symbol properties during the UPDATE process& n8 Q) v) @& }' {" x' {
1420580 CONSTRAINT_MGR INTERACTIV Constraint Manager crashes when displaying the Relative Propagation Delay worksheet& u1 y; E( r; F% x- ~
1420623 CONCEPT_HDL CREFER creferhdl fails with message std::bad_alloc on Windows and Linux
( r) q7 l) w' a2 ]5 l1421106 ALLEGRO_EDITOR DATABASE Get message "E- (SPMHDB-183): 'SHAPE' object may not exist on layer 'ETCH/WIRE'" when updating dyanmic shape.
& \1 ]2 ^. @0 b0 f+ _6 Y1421352 ALLEGRO_EDITOR EDIT_ETCH Application crashes when Create Fanout is executed with a blank end layer.; [# l3 C7 f; |$ b. m& ~3 {# J) L
1421769 ALLEGRO_EDITOR MANUFACT NC Drill legend behavior changed from S040 to S048& O/ n7 n$ p1 ~3 N* ?2 M2 z6 _
1422131 APD DXF_IF dxf error4 b1 [3 R4 ~: r( X- I
1422153 CONSTRAINT_MGR OTHER The display in cmDiffUtility is corrupted after a Match Group is removed
' s2 V6 u/ t9 b9 i6 `1422372 CONCEPT_HDL PDF Publish PDF-generated file: Unable to click links or copy in Javascript window
, a' j. ]& H" G% n6 f& n: F, k1422993 SIP_LAYOUT DIE_STACK_EDITOR Diestack Editor graphics depicts die stack incorrectly. The complete stack isn't shown# w/ x( l V' g1 I* z
1423268 SIP_LAYOUT SYMB_EDIT_APPMOD Update Die Extents causes Die layer change; M8 g1 I) F! I9 X+ w6 F6 c
1423539 ALLEGRO_EDITOR EDIT_ETCH Timing Vision crashes for board.
+ U4 |; D" e+ x7 \1 [1423988 ASI_SI GUI DesignLink system configuration file is not set automatically on SI-Base
( u! p( f8 b- o8 Q6 K$ Q& n1424053 SIP_LAYOUT ASSY_RULE_CHECK DRC info of "Acute Angle Merged Metal Check" reports the same via object to itself$ ~& u6 @9 W4 W' ^6 g" |0 u
1424415 GRE CORE 2 bundles are misbehaving during plan spatial.
H: N% E$ b( m" g% R! r* ~1424773 CONCEPT_HDL OTHER How to delete schematic-defined netgroups with locked members in the top-level block, }1 R' @5 h. {; ~
1425060 RF_PCB DISCRETE_LIBX_2A Miscellaneous enhancements requested for discrete library translator( l0 G8 i' J u6 W0 ]7 }) [. V" Z
1425592 F2B BOM Generating BOM in CSV format changes the value format8 N! C& \5 h: i" K0 n$ ^5 I% w
1426286 ALLEGRO_EDITOR EXTRACT Slotted hole within a footprint supported in STEP file
" K# ^! B/ C! M* x& _2 b4 ?1426593 CAPTURE DRC orcad Capture crashes on replaying DRC command.3 _- v+ H( c% `$ X
1426939 CONCEPT_HDL CORE Error message SPCOCN-2208 can be misinterpreted
9 X# m: W+ @6 | \: G* B' g9 ]3 q- S: m1427364 F2B PACKAGERXL Board does not backannotate and generates this message: ERROR (SPCOPF-2069): COMP_DEVICE_TYPE! j7 D. \) Y& h) l4 K6 r, M
1427690 CONCEPT_HDL PDF PDF Publisher on remote display hangs if run on a design with a missing component( N3 G) ^/ O; @8 N+ ^* f
1427721 CONCEPT_HDL CORE The copy paste command on text doesn't preserve the text size
3 ?) x5 p3 j5 m8 }; R% Q1428130 CONCEPT_HDL CORE LRM reports additional parts on schematic which were already synchronized with the cache ptf
3 o. ^2 \* `4 l5 l1428925 CONCEPT_HDL CORE Global signal is not selected as base if it is synonymed to local signal with ase suffix.
: q M, @+ w- T7 `/ D* H9 O. e! T1429526 ALLEGRO_EDITOR INTERFACES Export PDF is blank if lanscape mode is selected.
2 X9 ]% M9 A1 i) G1429840 SIP_LAYOUT SYMB_EDIT_APPMOD pin numbers are not applied if I have used library manager
+ g9 [# h2 w, u8 g" z1430098 ORBITIO ALLEGRO_SIP_IF The Die Pads and Vias around Die are missing when the SiP database is imported in ORbitIO; T4 t! o* j1 _( m$ u
1430564 ALLEGRO_EDITOR PLACEMENT moving group separates Place Bound from group 不好意下载上传都比较慢让大家久等了。下载链接 ：http://pan.baidu.com/s/1qWwYnNI
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发表于 2015-6-28 20:56
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