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更新内容： [( P7 o4 I5 Q' j7 ]; o4 W
DATE: 03-27-2015 HOTFIX VERSION: 046% s, g. N8 [. P( L$ ~# r
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0 `- R! O4 o1 R( J! t& [- ACCRID PRODUCT PRODUCTLEVEL2 TITLE
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4 v* q! `- V( d: j3 ]+ c) v; g1259541 SCM UI Cross probing function required between SCM and PCB Editor in 16.6
) z0 J9 m8 {1 Q5 @1281975 ADW LRM LRM reports numerous incorrect errors
* R" v' N; n0 o% y$ i% Q! D# _2 s1317937 CONSTRAINT_MGR OTHER cmDiffUtility shows incorrect results, if the order of gate information does not match
0 \! c( i# U1 `1327533 SIP_LAYOUT REPORTS Metal Usage Report fails for a layer that has cavities in SiP Layout
/ }. ~* [. T- f, ]) I, x1338084 PSPICE SLPS Use as default option grayed out in SLPS product choices window- c1 x5 u* q# x% ~
1353369 SCM OTHER Required support for semicolon in a key property value in ASA
5 O& k) d. Z2 F" {: g" ^1360269 SIP_LAYOUT REPORTS Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set
3 J4 V I+ m! k6 m1365435 CONSTRAINT_MGR OTHER The cmDiffUtility is not working with 16.6-s041
( s* j+ D4 A: h& N$ A1366012 CONSTRAINT_MGR CONCEPT_HDL Constraint Difference report shows NO_SHAPE_CONNECT property being deleted for all listed pins; }7 n% b) S# i; `
1371959 ALLEGRO_EDITOR DATABASE Running dbdoctor generates the error "Illegal database pointer encountered, Exiting DBDOCTOR"
{* Y8 r+ u5 J8 Z2 g7 n/ r1373478 PSPICE SIMULATOR PSpice Schedule command does not work correctly
0 E6 X& U% G! j5 p- w- y1373564 ASI_PI GUI Impedance results are incorrect in Power Feasibility Editor - Allegro Sigrity PI# R# c* i, H' i
1379240 APD PLACEMENT Symbol placement generates a false error about unit differences between the database and the symbol5 T/ E9 t- a3 F! X& _. d f$ y1 X
1379577 SCM UI Cross probing not working between SCM and CDNSIP& @9 I# U, L2 `5 R5 [6 p
1394297 PCB_LIBRARIAN CORE Text height on a symbol pin is retained only when Part Developer is launched with the PCB_LIBRARIAN_EXPERT license
! R9 w" d1 U" `, c) E- ?1394908 ALLEGRO_EDITOR DATABASE Database crashes on choosing "Show Element" on selected nets in PCB Editor
7 S3 T' L- i8 d7 |! `4 R$ L1395234 SIP_LAYOUT DXF_IF DXF file exported from SiP is not recognized by AutoCAD+ m. R a( m$ p9 E
1395541 ALLEGRO_EDITOR PLOTTING The Allegro PDF export function is not exporting phantom line type figures as they appear on the board
! }8 V {7 n- P; C* ~, a$ C1 @1395747 CONSTRAINT_MGR INTERACTIV With Constraint Manager open, rename refdes causes PCB Editor to crash.
/ R+ w5 ?7 Y+ g0 c1396138 FSP FPGA_SUPPORT Support required for FPGA device XCVU190-2FLGB2104E) z3 O1 g* f- n! w/ Q0 M/ |) y B# I9 x
1396915 APD STREAM_IF The stream out command with mirror geometry option does not include mirrored results in the generated output.( X. l( `2 t: M# J
1396990 FSP FPGA_SUPPORT Support required for FPGA device XC7A50T-L2CSG325E
8 m1 _: z0 R& G1398184 ALLEGRO_EDITOR MANUFACT Mismatch in backdrill data with IPC-2581 export* F' P$ ?) Q2 l: g) n
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发表于 2015-3-28 23:54
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发表于 2015-3-29 20:20