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2023-10-13 15:24 |
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签到天数: 3 天 [LV.2]偶尔看看I
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更新内容：; n$ w0 L8 V8 H
DATE: 03-27-2015 HOTFIX VERSION: 046 K! v; o# I6 F1 A0 J u3 s5 T
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1259541 SCM UI Cross probing function required between SCM and PCB Editor in 16.6
/ l) X3 l) O1 E8 u1281975 ADW LRM LRM reports numerous incorrect errors
5 N" t1 b' y4 @) ^; I7 O8 l x* ^2 x1317937 CONSTRAINT_MGR OTHER cmDiffUtility shows incorrect results, if the order of gate information does not match; {. d# X1 i e5 X3 l
1327533 SIP_LAYOUT REPORTS Metal Usage Report fails for a layer that has cavities in SiP Layout
! V6 _: q6 ~, o1338084 PSPICE SLPS Use as default option grayed out in SLPS product choices window/ Y5 |4 ^$ ~: X9 F; `7 S& h8 a
1353369 SCM OTHER Required support for semicolon in a key property value in ASA8 V, N& c; H2 c! J/ ?
1360269 SIP_LAYOUT REPORTS Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set
# V% C9 ]2 N; g8 J/ B' w1365435 CONSTRAINT_MGR OTHER The cmDiffUtility is not working with 16.6-s041# ?) ~) u8 c! a( M. ?
1366012 CONSTRAINT_MGR CONCEPT_HDL Constraint Difference report shows NO_SHAPE_CONNECT property being deleted for all listed pins" ?1 [! u) T8 A! e0 |& s8 T! F
1371959 ALLEGRO_EDITOR DATABASE Running dbdoctor generates the error "Illegal database pointer encountered, Exiting DBDOCTOR"
. B# S% m) Z9 H7 h* B; h3 e1373478 PSPICE SIMULATOR PSpice Schedule command does not work correctly
9 f- p$ G( ~; B# M: [9 f" K$ N1373564 ASI_PI GUI Impedance results are incorrect in Power Feasibility Editor - Allegro Sigrity PI
, F, [. D* k% [. G1 A1379240 APD PLACEMENT Symbol placement generates a false error about unit differences between the database and the symbol8 R- n2 X" Y# [. n
1379577 SCM UI Cross probing not working between SCM and CDNSIP4 R( n3 I+ i' k5 L4 }% R
1394297 PCB_LIBRARIAN CORE Text height on a symbol pin is retained only when Part Developer is launched with the PCB_LIBRARIAN_EXPERT license, r" _3 |+ P( B9 C
1394908 ALLEGRO_EDITOR DATABASE Database crashes on choosing "Show Element" on selected nets in PCB Editor
8 `! n! ?. n* D4 f1395234 SIP_LAYOUT DXF_IF DXF file exported from SiP is not recognized by AutoCAD; L7 F" V& [) C* p
1395541 ALLEGRO_EDITOR PLOTTING The Allegro PDF export function is not exporting phantom line type figures as they appear on the board
l. \* {( J: }. H- Q: b6 \1395747 CONSTRAINT_MGR INTERACTIV With Constraint Manager open, rename refdes causes PCB Editor to crash.2 {3 m: o( U6 V, x7 c
1396138 FSP FPGA_SUPPORT Support required for FPGA device XCVU190-2FLGB2104E; |4 ^# a7 `! d3 x
1396915 APD STREAM_IF The stream out command with mirror geometry option does not include mirrored results in the generated output. \+ ^ y9 l$ K7 }7 G, ~& l: c
1396990 FSP FPGA_SUPPORT Support required for FPGA device XC7A50T-L2CSG325E) l1 n1 A6 I8 T4 H$ V
1398184 ALLEGRO_EDITOR MANUFACT Mismatch in backdrill data with IPC-2581 export/ E6 q2 `3 s5 Y5 }8 B ^5 {
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发表于 2015-3-28 23:54
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发表于 2015-3-29 20:20