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本帖最后由 zgyzgy 于 2015-3-15 14:42 编辑
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+ l% t4 X: S0 M. ?1 eDATE: 03-13-2015 HOTFIX VERSION: 045& Q2 w L# c7 H3 I- W- K
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1308671 concept_HDL PDF Pivotal symbol on Hierarchical Split Symbol bodies needs to be hidden in the generated PDF3 R/ q+ i- v& ?5 F
1349899 Pspice NETLISTER PSpice: Getting different simulation results in versions 16.5 and 16.6
& j# F6 Y. H4 ]; U1355271 FSP DE-HDL_SCHEMATIC FSP generating incorrect connectivity information in HDL
0 r w7 K- C% X z! j1370402 ADW TDA TDO does not use the specified name for creating the local work area.
2 G" S" {$ b$ \, R1371281 CONCEPT_HDL CONSTRAINT_MGR It takes 10 minutes to launch Constraint Manager% X6 |, z, u4 j4 G
1372480 CONCEPT_HDL CORE How do I get ASA to recognize changes made to a schematic block?
8 r, V6 P' X1 X6 Y1 d1372939 CONCEPT_HDL CORE Save Hierarchy and Save All do not resolve the duplicate refdes issue in a SIZEd part
V; a+ M1 [! A5 A, E) o2 V1375265 ASI_SI OTHER allegro Sigrity SI to XtractIM translation failed with a workspace file opening error
" u. [. m/ @" }$ l, Y1376225 SIP_LAYOUT DIE_ABSTRACT_IF 'Refresh co-design die' operation fails with "incorrect number of ETCH subclasses defined" message$ Z: f0 k( [, j) Z$ ~# d! a
1376644 ALLEGRO_EDITOR mentor Command line mbs2brd still needs SI licenses
3 S$ g [0 u1 {% t/ _- W1376846 SIP_LAYOUT IC_IO_EDITING Running the Show IC Details command generates a drawing/symbol extents error, then SiP crashes% E4 I' W' @' _7 X0 w
1377297 ALLEGRO_EDITOR EDIT_ETCH PCB Editor crashes when using the Remove Tuning command
- W' x1 P ~" ?- I" k- l4 |1377587 CONCEPT_HDL MARKERS The marker file cannot be loaded using the console command "_! markers load <filename.mkr>".
' A0 f! n. _: h9 I8 R1377711 TRANSLATOR SPDLINKS Unable to open an MCM file in XtractIM from APD7 b3 i; L9 Q- F$ a* A. }
1377962 CONCEPT_HDL CORE If an instantiated part is removed from the library, DE-HDL hangs while reading the .xcon file
3 q/ w/ b! m8 L( f5 j+ L1378032 ALLEGRO_EDITOR REPORTS Report command and batch mode give different Waived DRC Report results in PCB Editor6 c. q: S/ b9 L
1379797 F2B PACKAGERXL Connections are missing in the generated netlist& k% u% S# X' X Q6 _8 Z' l
稍后附上链接。。。。。。
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