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DATE: 02-13-2015 HOTFIX VERSION: 043
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CCRID PRODUCT PRODUCTLEVEL2 TITLE$ |6 V+ G7 E4 ?" Y; x3 D
===================================================================================================================================0 ^; o1 R0 Q+ \2 Y; | ]
1259909 ADW DSN_FLOW Unlike Project Manager, parts cannot be copied from one design to another using ADW8 G; ]; k% n# G; z" @
1341092 ALLEGRO_EDITOR MANUFACT Export > PDF should show drill holes if the Filled option is selected8 p* [$ |/ y# @8 S- o
1356711 SPIF OTHER Unable to use PCB Router function with PA5700 license.
+ n( n; h! `" T* z1357880 ALLEGRO_EDITOR INTERFACES Incorrect Step model view in Step Package mapping window
* _0 V/ } {! z1362132 ALLEGRO_EDITOR DATABASE X hatch shape with cell High shows shape boundary error b+ u; |7 ^+ C4 V, H z
1362641 ALLEGRO_EDITOR INTERACTIV Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
$ I% n8 N2 M4 N8 }1 m1362771 ALLEGRO_EDITOR EDIT_ETCH Running AiDT displays an error; the tool crashes on subsequent runs
! _6 _$ g+ X8 \' ]1363908 SIP_LAYOUT PLACEMENT SiP Layout crashes when refreshing symbols
2 F, G) Z( l+ w' V7 g1364113 ALLEGRO_EDITOR MANUFACT NC drill output does not comply with NC Parameters if the unit is inconsistent
" s5 i; w6 f4 |+ ? k* H5 L6 x1364146 PSPICE SIMULATOR Simulating the attached Design gives 'RPC Server is unavailable' Error.( k2 ]7 j% o8 a# X9 ]
1364209 ALLEGRO_EDITOR INTERFACES STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
7 k; z- q9 |+ e; v1364329 CONCEPT_HDL CORE Show Physical Net Name causing netlisting errors
, \8 }7 u% t+ k) P$ M: \1364367 PCB_LIBRARIAN IMPORT_VIEWLOGIC viewlogic2con translator does not complete
7 t4 M% H, H$ H4 v* [1364771 ALLEGRO_EDITOR MANUFACT Incorrect Gerber created for mounting holes
9 N* M. U5 |5 B3 r, R; @1366415 CONCEPT_HDL CORE global navigation not working for few buses in the design# W5 l% g- |, _3 V3 `
1367650 SIP_LAYOUT IC_IO_EDITING Add Respace command to Symed app mode for I/O drivers0 r8 I9 `8 n0 J8 Y
1368246 SIP_LAYOUT OTHER Cannot delete die(s) that were placed manually in a design
( c3 e3 i5 g" U4 B9 E/ o! A1368889 ALLEGRO_EDITOR INTERFACES Unable to export incremental updates of the IDX baseline file, t3 R" N, J3 A' K/ a3 O/ z
1369177 SIP_LAYOUT OTHER Add a new command to create a bounding shape
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DATE: 01-30-2015 HOTFIX VERSION: 042
( }; U: L" d! Z8 P===================================================================================================================================
+ W( Y" V& u' L- nCCRID PRODUCT PRODUCTLEVEL2 TITLE% n- U9 i/ z" H9 n+ ^5 S! ~
===================================================================================================================================
: {& K/ M3 R+ d7 i/ z1334361 ALLEGRO_EDITOR INTERACTIV ZCopy should be able to copy multiple clines
. h5 }7 _0 p" z1348389 CIS PART_MANAGER Update selected part status should re-query every time the command is run$ |4 D7 D( i; _% ^1 O& x2 E. j, M
1349342 ALLEGRO_EDITOR EDIT_ETCH Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
7 V5 }/ [: u3 f5 y# @1349849 CIS OTHER Capture crashes on generating variant reports" [5 C% d2 z# e: _2 N4 A
1349983 PSPICE SIMULATOR Simulation aborts if save data option is greater than 1 sec
, u9 B- `1 I0 {. g8 F1350477 PSPICE SIMULATOR RPC server is unavailable: ]! J' I& \# y9 d' I/ i
1353830 SIG_INTEGRITY SIMULATION xtalk analysis leads to crash
8 q \! D/ F& A$ W+ c: F5 w& e: R* B1354644 ALLEGRO_EDITOR EXTRACT Extracta does not extract a value for specific property
1 o9 k6 u! s+ N) x( x; j2 c1355337 ALLEGRO_EDITOR EDIT_ETCH Windows 8 Route Connect produces Buffer error.
+ @! m& q- g0 H2 @/ H! z: I* A% \( E1355522 SIP_LAYOUT IC_IO_EDITING Option to select reference point for alignment should be available when aligning single drivers0 X. R7 J' d' m! b0 `6 }
1355737 ALLEGRO_EDITOR EDIT_ETCH No available buffer identifiers cause loss of control in a routing phase
1 ^0 {: L9 d* f+ h. \5 ` F5 L1356373 ALLEGRO_EDITOR DRC_CONSTR Design is crashing when attempting to update the DRCs.
! W/ V+ t' @4 c/ e+ g+ q8 r1356684 SIP_LAYOUT SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to7 `# u2 c) `& V, f5 }+ d
1358383 ALLEGRO_EDITOR MODULES mdd file is not created correctly
" B4 h# f) F4 y2 Q' L1358558 CONCEPT_HDL GLOBALCHANGE "Global Component Change" could not update parts.2 P; F" v/ G* j: V9 |- b3 o4 `
1359780 ALLEGRO_EDITOR EDIT_ETCH The board database crashes on using Route Connect after some editing of traces., ]6 m- W9 Q2 o: F7 z5 Q: Q( ~7 `
1360416 SIP_LAYOUT OTHER SiP Design Variant not being created on the design- Y( Q G2 E V) l0 m @
1360630 FSP ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
9 R7 D3 c8 n$ x4 [6 K, m1361157 ALLEGRO_EDITOR GRAPHICS 3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.. T( ?8 ^* f1 t+ [; Z7 {' U+ {* u4 v
1361925 FSP DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.; ^+ C- n3 e* w+ Q+ A
1362865 CONSTRAINT_MGR OTHER Import logic is not creating model-defined differential pairs.
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发表于 2015-2-15 23:37
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