Hotfix_SPB16.60.043_wint_1of1

zgyzgy

http://pan.baidu.com/s/1fehWy 年前分享下43。。。。。。

pzt648485640

DATE: 02-13-2015   HOTFIX VERSION: 043
5 L  q3 C- F: ^- n===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1259909 ADW            DSN_FLOW         Unlike Project Manager, parts cannot be copied from one design to another using ADW
' e0 ~7 Z( A) j3 h/ I1341092 ALLEGRO_EDITOR MANUFACT         Export > PDF should show drill holes if the Filled option is selected
1356711 SPIF           OTHER            Unable to use PCB Router function with PA5700 license.
1357880 ALLEGRO_EDITOR INTERFACES       Incorrect Step model view in Step Package mapping window
1362132 ALLEGRO_EDITOR DATABASE         X hatch shape with cell High shows shape boundary error
1362641 ALLEGRO_EDITOR INTERACTIV       Unwanted apostrophes are added to ads_sdart and few other variables under File_management in User Preference
1362771 ALLEGRO_EDITOR EDIT_ETCH        Running AiDT displays an error; the tool crashes on subsequent runs
1363908 SIP_LAYOUT     PLACEMENT        SiP Layout crashes when refreshing symbols
4 y7 v( ]" g' v) @+ t. U* M1 d1364113 ALLEGRO_EDITOR MANUFACT         NC drill output does not comply with NC Parameters if the unit is inconsistent
+ z* b1 b% _/ B1364146 PSPICE         SIMULATOR        Simulating the attached Design gives 'RPC Server is unavailable' Error.
# ~; b7 u+ \, p1364209 ALLEGRO_EDITOR INTERFACES       STEP export: Allow for zero height and instance height change with PLACE_BOUND_TOP/BOTTOM
1364329 CONCEPT_HDL    CORE             Show Physical Net Name causing netlisting errors
1364367 PCB_LIBRARIAN  IMPORT_VIEWLOGIC viewlogic2con translator does not complete
  R+ |; W% [/ n% _0 u9 `* W0 f1364771 ALLEGRO_EDITOR MANUFACT         Incorrect Gerber created for mounting holes
1366415 CONCEPT_HDL    CORE             global navigation not working for few buses in the design
1367650 SIP_LAYOUT     IC_IO_EDITING    Add Respace command to Symed app mode for I/O drivers
1368246 SIP_LAYOUT     OTHER            Cannot delete die(s) that were placed manually in a design
; t3 A! _0 J/ a7 R( K, o) m5 `1368889 ALLEGRO_EDITOR INTERFACES       Unable to export incremental updates of the IDX baseline file
1369177 SIP_LAYOUT     OTHER            Add a new command to create a bounding shape
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DATE: 01-30-2015   HOTFIX VERSION: 042
===================================================================================================================================
1 V1 B: w8 l$ E2 k& }& OCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
0 s+ W: h7 g2 t/ a9 P# I===================================================================================================================================
' ~7 e, Q2 U) y* @* F3 T! T) {1334361 ALLEGRO_EDITOR INTERACTIV       ZCopy should be able to copy multiple clines
, M3 W, J4 [. R" I1348389 CIS            PART_MANAGER     Update selected part status should re-query every time the command is run
; f- x5 \8 f, P6 {' ]6 J; _1349342 ALLEGRO_EDITOR EDIT_ETCH        Need information on how to resolve (SPMHA1-170): No available buffer identifiers.
1349849 CIS            OTHER            Capture crashes on generating variant reports
( q2 @6 ]- c1 Q8 K# h; z& l$ \! g1349983 PSPICE         SIMULATOR        Simulation aborts if save data option is greater than 1 sec
, r, U+ G9 {, u1350477 PSPICE         SIMULATOR        RPC server is unavailable
1353830 SIG_INTEGRITY  SIMULATION       xtalk analysis leads to crash
1354644 ALLEGRO_EDITOR EXTRACT          Extracta does not extract a value for specific property
1355337 ALLEGRO_EDITOR EDIT_ETCH        Windows 8 Route Connect produces Buffer error.
% M5 i6 M% F8 G1355522 SIP_LAYOUT     IC_IO_EDITING    Option to select reference point for alignment should be available when aligning single drivers
1355737 ALLEGRO_EDITOR EDIT_ETCH        No available buffer identifiers cause loss of control in a routing phase
1356373 ALLEGRO_EDITOR DRC_CONSTR       Design is crashing when attempting to update the DRCs.
1356684 SIP_LAYOUT     SYMB_EDIT_APPMOD Enhance highlight of swappable pins excluding the pin to be swapped to
1358383 ALLEGRO_EDITOR MODULES          mdd file is not created correctly
1358558 CONCEPT_HDL    GLOBALCHANGE     "Global Component Change" could not update parts.
- t; @! M4 ]; q* e" v4 x1359780 ALLEGRO_EDITOR EDIT_ETCH        The board database crashes on using Route Connect after some editing of traces.
% L9 x/ n/ X; R: g4 Q1360416 SIP_LAYOUT     OTHER            SiP Design Variant not being created on the design
: |5 @  B$ _) Y) \5 Y% w( n2 W1360630 FSP            ALLEGRO_INTEGRAT For Fixed Internal and Fixed External nets, FSP shows net schedule difference in PCB Editor
: b% Q7 [/ C. d3 i; W1361157 ALLEGRO_EDITOR GRAPHICS         3D view of footprint with STEP model not correct, although it shows correctly when footprint is placed on board file.
% K" ?9 p( S! ^1361925 FSP            DE-HDL_SCHEMATIC Port is not connected for the nets having netname as NC.
1362865 CONSTRAINT_MGR OTHER            Import logic is not creating model-defined differential pairs.
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hensonman

补丁装到一半提示选择next disk，是否有几个补丁要一起装

wolfshiao

感謝樓主的分享,
$ C9 S- k4 ]* c1 D雖然沒跟著更新,但也是要感謝的啦!!

mengshang

43更新已趋近稳定了。

amaryllis

年前居然还有福利，cadence还蛮拼的。楼主V5

qiuzhang

谢谢，辛苦了

rongzhai

多谢分享

Maxim

谢谢，辛苦了

hensonman

这补丁好大..

wangshilei

niu

muller1981

感謝樓主的佛心分享!
4 c. H' K2 S5 m+ F- e: H大感謝!~

hydf

谢谢，新春快乐！

cxt668

更新的也太快了一点，坐等17.0版发布

nbxiong

坐等17.0版发布