Hotfix_SPB16.60.040_wint_1of1.exe 更新

zgyzgy

. P! A0 N, i" w$ P5 ^5 j9 r
SPB16.60稍后跟链接           链接：http://pan.baidu.com/s/1o69LWDk 密码：v1l5

DATE: 12-12-2014   HOTFIX VERSION: 040
===================================================================================================================================
CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
. N' v7 y. T) u0 R( O9 N* g===================================================================================================================================
3 \9 ]5 {3 X# @6 M& ?! P; m577694  allegro_EDITOR OTHER            Need to retain padstack edits during "Refresh Symbols"
- V( ?* K. W& q$ D5 g- ~' @. t1105280 FSP            MODEL_EDITOR     Negative Voltage leads to 'Internal error. Invalid voltage value -12 specified for pin'
5 g! b) ?6 f& l. L. ~. d1198148 FSP            OTHER            In the Symbol Setup form instances instantiated multiple times must be customized individually
, w# ]: u5 n2 M3 |% z& C1200015 concept_HDL    CORE             module_order.dat is generated for sym_n view automatically
1275209 Pspice         NETLISTER        PSpice is not considering 3K9 as 3.9K if inside a condition in PSpice template
! u; C, H. Z9 C' ~0 z1297335 SPECCTRA       FANOUT           Wrong fanout created in PCB Editor on using the Route Automatic option.
- K; c/ e( r$ E* d8 m1316637 CONCEPT_HDL    PDF              PublishPDF does not set arc lines to the defined line width setting
1320581 ALLEGRO_EDITOR OTHER            Dangling line listed in Dangling Line report but no line exists.
: Y, H4 x1 U* K( c; v0 X( }1326104 CONCEPT_HDL    CORE             Pin dots, pin text do not stay on grid in symbol editor on moving/copying.
7 t4 y% G- Q$ i/ C" U1329848 CONSTRAINT_MGR CONCEPT_HDL      Export Excel from DE-HDL CM displays 'Server busy' message.
2 u" U! o& B! W. x( ?; t1330044 CONSTRAINT_MGR OTHER            Need command line equivalent of cmDiffUtility to save reports as HTML
" a' K  m: U& h6 H- \; O- Y. d# [1330122 SIP_LAYOUT     PLACEMENT        When placing IC type symbols in SiP they are being placed as Wire Bond instead of Flip Chip.
1330930 CONCEPT_HDL    CORE             Hyperlink in attributes window not working.
1336086 SIP_LAYOUT     MANUFACTURING    If a design has bondfingers at a certain angle/position the tool does not create a soldermask opening
4 f( Y4 z7 F' T" V' n1338610 MODEL_INTEGRIT TRANSLATION      IBIS to DML failed with incorrect error message.
1338925 ALLEGRO_EDITOR MANUFACT         Need a 16.5 route file option in SPB 16.6.
0 ^  ]6 W( Y! d5 W9 n4 p1339672 CONCEPT_HDL    CORE             Editing a symbol in PDV results in error (SPCOCN-1731)
3 f7 p$ U7 L( V0 e1339987 ALLEGRO_EDITOR skill            axlFormCreate embeddedForm is not working as expected
* l- S& f$ g5 F8 H+ h( N5 x1339989 PCB_LIBRARIAN  LIBUTIL          Con2con exits if Global section of PTF file has NC_PINS
1340342 F2B            DESIGNVARI       DE-HDL crashes when trying to use Variant commands
1340360 ALLEGRO_EDITOR EDIT_ETCH        On running the AiDT command, if Total Etch Length is defined directly on an XNet, PCB Editor crashes.
0 m3 W" x/ M7 C* }) Z: W9 v1340854 CONSTRAINT_MGR CONCEPT_HDL      Component properties are lost during backannotation
1341096 SIP_LAYOUT     ASSY_RULE_CHECK  ADRC rule 'Wire to Pad Optical Short' gives wrong results
- z  ]& X$ D; ]2 x4 Q; v1341330 ALLEGRO_EDITOR DRC_CONSTR       Spacing rules not followed if bond_pad is set to bond_finger
! M& O2 `8 ]0 u& ~6 D5 Y/ v( x! R  f1342705 ALLEGRO_EDITOR INTERFACES       IDX incremental bend areas need delete processed first before adds
1342910 FSP            SETTINGS         Unable to remove "Don't Use Banks" setting.
1343076 SIG_INTEGRITY  OTHER            'orcad PCB Professional' tier should not allow Differential Pair extraction
. `6 L9 }) P" Z) z: N1343239 PCB_LIBRARIAN  VERIFICATION     Con2con reporting errors against the wrong primitive
8 d+ g; c% E4 Z0 l: [# t1343257 SCM            SETUP            In SCM, unable to add termination to design.
1343403 CONCEPT_HDL    CORE             Return code in Search_History prevents DE-HDL launch.
/ U, S" x# J+ @) P. @7 d3 a1 `: Z1343749 CONCEPT_HDL    CORE             Global Navigate does not always respond
1343870 ALLEGRO_EDITOR DATABASE         Import Logic changes VIA net names to GND
1343949 FSP            IMPORT_ALLEGRO   Import Instances from PCB Editor does not import FPGA model
8 Z6 T5 i7 U5 j+ A% a1344265 CONCEPT_HDL    CORE             DE-HDL crashes on viewing page search
1 a7 v8 i, B' s8 F. v1344413 SIP_LAYOUT     DIE_GENERATOR    When composing a die From Geometry the die pads are shifting.
1344745 ALLEGRO_EDITOR EXTRACT          Need information about the changes in the format of the report generated using axlExtractToFile()
1346277 SIP_LAYOUT     DIE_ABSTRACT_IF  Shape cannot be read when sip_symed_codesign is set.
1346318 CONSTRAINT_MGR OTHER            cmDiffUtility shows "unrelease_unrelease.." message and stops
1346621 ASI_PI         GUI              Sigrity tools shown in PI Base Analyze menu regardless of option selected
& k+ h0 C* B& M1347103 ALLEGRO_EDITOR INTERFACES       Step mapping - 3D view for mechanical symbol