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发表于 2014-11-16 10:34
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1 M9 J! L4 K5 X7 I5 ODATE: 11-14-2014 HOTFIX VERSION: 039. w3 @8 t3 F! s4 ]$ s
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CCRID PRODUCT PRODUCTLEVEL2 TITLE
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1213239 FLOWS PROJMGR SPI_ERROR: Missing closing quote at line 41 in""
& {: J; k7 L9 t1 X, l9 m; e1301262 SPIF OTHER When creating .dsn file for designs containing netclasses with net groups, PCB Editor stops responding.1 a3 b) V, |# @: P$ k+ {' s
1301469 CONCEPT_HDL CORE DE-HDL Import Design - Need a directive to enable the "Retain Hard Packaging Information" option by default
) l1 z0 @( W( P$ _1309535 SYSTEMSI ENG_PBA PA5700: Cannot print, save, or post process SI analysis reports6 i! w- W5 Y% O) I1 A! _% S
1317019 SIG_INTEGRITY LIBRARY Buffer model for pins not changing correctly when multiple DML files are present in working directory.- |; F* A( C+ u& r# {1 q4 i+ }
1318452 ALLEGRO_EDITOR DATABASE Derive Connectivity does not update connections; DRC errors thrown6 `- b8 A9 p5 C, ?! c U; c, u4 O
1318610 CONCEPT_HDL CORE DE-HDL does not re-validate/re-read DML files on disk upon launching Constraint Manager& o( N# o) o! m: i/ M" o2 t7 ^# c3 F
1320997 CAPTURE SCHEMATIC_EDITOR Copy paste of multiple images are stacked in same place.3 F$ U+ n1 I5 y
1321377 FSP GUI FSP crashes while performing copy-paste operations between different arrays in the Rule text editor% U: g+ x( l# w% ~7 z
1321513 ALLEGRO_EDITOR SYMBOL Preview not available for DRA
9 e' N2 {; A, X9 s1324479 ALLEGRO_EDITOR OTHER Option specified in license_packages_allegro.txt file but missing in license server causes Segmentation fault on LINUX
- ?4 Y3 r U3 Q% Y1327962 FSP MODEL_EDITOR Need ability to select multiple pins in the Preview area of Rule Editor( I1 O5 k! m2 X |
1328633 CONCEPT_HDL CORE On running Save All, changes were partially saved before DE-HDL crashed." Q2 C, ?* P4 O X6 p+ n
1328921 ALLEGRO_EDITOR DATABASE Running Derive Connectivity followed by Database Check throws SPMHUT-17 error7 l9 t$ R( D7 _- }
1330029 CONCEPT_HDL CORE PIN_TYPE and PINUSE attributes not updated consistently in DE-HDL design3 w& R7 C+ c- z
1330580 SIP_LAYOUT SYMB_EDIT_APPMOD When adding a pin using the Symbol Editor the Pin Name is being changed if duplicated" f: E9 ]- J2 X
1331028 CONCEPT_HDL CHECKPLUS Rules Checker fails on DE-HDL component.
@ ?" S% t& |9 s I7 ^, `1331051 ALLEGRO_EDITOR INTERFACES Soldermask layer is mapped to both Soldermask solderPaste and Miscellaneous Image Layers columns using IPC-2581B+ _) x/ m/ l% @. u5 g
1333127 CONCEPT_HDL CORE Sheet number in the new window is only the block-level number and not the design-level number
1 I2 E; } c% `* K1333591 SIP_LAYOUT SKILL Difference in behavior for padstack replace using axlPadstackReplace and command Replace Padstack
" D1 `+ e9 X- r5 e% r, A1333896 ASI_SI OTHER signoise -f and -k options don't work for net names with consecutive underscores.
/ @5 E) F2 Q. l# r5 ^1333982 ALLEGRO_EDITOR ARTWORK ARTWORK: Coordinates of the hole get shifted by the "Draw holes only" option./ s# G- M) V. {
1334302 CONSTRAINT_MGR SCHEM_FTB Import Logic - Import changes only or Overwrite current constraints fails to update signal models.
9 z; w3 U: {- Q6 e6 N9 h% p1335276 CONCEPT_HDL OTHER On selecting objects near the schematic page border, the border is also selected
1 Y' ^+ e+ a" y% V4 g1 S9 T) |1336322 CONCEPT_HDL CORE DE-HDL does not open with maximized window.2 |5 n4 P6 @1 \9 C" W
1336783 PCB_LIBRARIAN IMPORT_EXPORT con2cap fails to export the part to OrCAD Capture format |
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发表于 2014-11-16 10:30
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发表于 2014-11-16 23:52
