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发表于 2014-11-16 10:34
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DATE: 11-14-2014 HOTFIX VERSION: 039
! s5 j5 B/ N. l1 [: {% e$ y===================================================================================================================================
; J6 K1 }+ Q6 f* |4 q+ Y% s- }CCRID PRODUCT PRODUCTLEVEL2 TITLE7 f( m, u1 Q5 E( I" o \; S
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1213239 FLOWS PROJMGR SPI_ERROR: Missing closing quote at line 41 in""
& E0 X, a: j9 {2 k& T3 ~1301262 SPIF OTHER When creating .dsn file for designs containing netclasses with net groups, PCB Editor stops responding.' n8 p/ R5 y z5 l; w
1301469 CONCEPT_HDL CORE DE-HDL Import Design - Need a directive to enable the "Retain Hard Packaging Information" option by default
1 F8 T3 Q: l7 P: _1309535 SYSTEMSI ENG_PBA PA5700: Cannot print, save, or post process SI analysis reports
& @& U. _* M5 Q1 l/ L1317019 SIG_INTEGRITY LIBRARY Buffer model for pins not changing correctly when multiple DML files are present in working directory.
9 g D5 k; U$ d4 F" p8 Z/ `8 I1318452 ALLEGRO_EDITOR DATABASE Derive Connectivity does not update connections; DRC errors thrown
5 h0 B7 t p# B$ E' j b1318610 CONCEPT_HDL CORE DE-HDL does not re-validate/re-read DML files on disk upon launching Constraint Manager- _5 ^* Z) D- m
1320997 CAPTURE SCHEMATIC_EDITOR Copy paste of multiple images are stacked in same place.
8 A# x* u! X" \1321377 FSP GUI FSP crashes while performing copy-paste operations between different arrays in the Rule text editor+ _; O( j7 @/ y$ R
1321513 ALLEGRO_EDITOR SYMBOL Preview not available for DRA7 `. w, q; ]' X5 V/ ], [8 h
1324479 ALLEGRO_EDITOR OTHER Option specified in license_packages_allegro.txt file but missing in license server causes Segmentation fault on LINUX
) q& ?# t* e5 t$ g( m# G5 C9 L0 a1327962 FSP MODEL_EDITOR Need ability to select multiple pins in the Preview area of Rule Editor
* i# T- J. n, F% b1328633 CONCEPT_HDL CORE On running Save All, changes were partially saved before DE-HDL crashed.) }5 x J/ c! n, ]# {1 ^1 _
1328921 ALLEGRO_EDITOR DATABASE Running Derive Connectivity followed by Database Check throws SPMHUT-17 error
1 u3 u0 @$ q/ n% M% E1330029 CONCEPT_HDL CORE PIN_TYPE and PINUSE attributes not updated consistently in DE-HDL design1 \" a$ Y- k2 _) k' `3 U4 P# U+ u: d
1330580 SIP_LAYOUT SYMB_EDIT_APPMOD When adding a pin using the Symbol Editor the Pin Name is being changed if duplicated
: ?5 s) U$ \, n* l1 N' H( Z' z5 i. T1331028 CONCEPT_HDL CHECKPLUS Rules Checker fails on DE-HDL component.. V1 ?, c" |& K# L( B
1331051 ALLEGRO_EDITOR INTERFACES Soldermask layer is mapped to both Soldermask solderPaste and Miscellaneous Image Layers columns using IPC-2581B: M, R! y- z! R5 t1 G. r6 F
1333127 CONCEPT_HDL CORE Sheet number in the new window is only the block-level number and not the design-level number
/ `8 Y) Y6 f( M7 w9 E2 s n1333591 SIP_LAYOUT SKILL Difference in behavior for padstack replace using axlPadstackReplace and command Replace Padstack
, o/ G# F+ G0 C& ~$ j' k! f1333896 ASI_SI OTHER signoise -f and -k options don't work for net names with consecutive underscores." U5 S0 W7 M- [ y
1333982 ALLEGRO_EDITOR ARTWORK ARTWORK: Coordinates of the hole get shifted by the "Draw holes only" option.5 n' L* h: H$ _ t0 \, @
1334302 CONSTRAINT_MGR SCHEM_FTB Import Logic - Import changes only or Overwrite current constraints fails to update signal models.
( r7 }, B4 H- U- f1335276 CONCEPT_HDL OTHER On selecting objects near the schematic page border, the border is also selected% k: _4 |& c6 l
1336322 CONCEPT_HDL CORE DE-HDL does not open with maximized window.
' w8 b6 _& C% K9 z* m1 }1336783 PCB_LIBRARIAN IMPORT_EXPORT con2cap fails to export the part to OrCAD Capture format |
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发表于 2014-11-16 10:30
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发表于 2014-11-16 23:52
