|
|
推荐
楼主 |
发表于 2014-11-16 10:34
|
只看该作者
5 w2 ?, N( u U# l0 q9 wDATE: 11-14-2014 HOTFIX VERSION: 039; r% s( M P9 v* N* W
===================================================================================================================================: s& w" M( [9 Z3 ^) P8 M t
CCRID PRODUCT PRODUCTLEVEL2 TITLE# X- p8 c x0 G* H1 N
===================================================================================================================================- s, J0 u3 p! J9 _) y
1213239 FLOWS PROJMGR SPI_ERROR: Missing closing quote at line 41 in""
; d7 V. Z5 {; `! _8 W1301262 SPIF OTHER When creating .dsn file for designs containing netclasses with net groups, PCB Editor stops responding.' ?( E1 n- N) c4 r' }' `* }# }7 x3 Q0 _
1301469 CONCEPT_HDL CORE DE-HDL Import Design - Need a directive to enable the "Retain Hard Packaging Information" option by default: x3 T7 B% n2 J' f
1309535 SYSTEMSI ENG_PBA PA5700: Cannot print, save, or post process SI analysis reports
( w- n$ P q+ Q+ Y5 `2 @1317019 SIG_INTEGRITY LIBRARY Buffer model for pins not changing correctly when multiple DML files are present in working directory.
5 G9 I4 H% Z4 \4 [* P( O1318452 ALLEGRO_EDITOR DATABASE Derive Connectivity does not update connections; DRC errors thrown6 @$ E' O' E7 U2 ? I
1318610 CONCEPT_HDL CORE DE-HDL does not re-validate/re-read DML files on disk upon launching Constraint Manager
* `4 d0 t# [8 q7 C1320997 CAPTURE SCHEMATIC_EDITOR Copy paste of multiple images are stacked in same place." o F- e `: G$ a- x! @1 {: x. n
1321377 FSP GUI FSP crashes while performing copy-paste operations between different arrays in the Rule text editor
. Y$ g6 ]- e; T3 V1321513 ALLEGRO_EDITOR SYMBOL Preview not available for DRA
2 f9 b4 A7 l2 A& Q3 T @) M% c# C% c |1324479 ALLEGRO_EDITOR OTHER Option specified in license_packages_allegro.txt file but missing in license server causes Segmentation fault on LINUX) ~1 }% W. i5 E+ f6 s/ ]- M
1327962 FSP MODEL_EDITOR Need ability to select multiple pins in the Preview area of Rule Editor/ U; P( F! b: Z: n( `. p$ f. e
1328633 CONCEPT_HDL CORE On running Save All, changes were partially saved before DE-HDL crashed.
& l" a' C4 F! `1328921 ALLEGRO_EDITOR DATABASE Running Derive Connectivity followed by Database Check throws SPMHUT-17 error3 k% _7 {( r4 @6 M/ K8 C- U' p: b& t; p
1330029 CONCEPT_HDL CORE PIN_TYPE and PINUSE attributes not updated consistently in DE-HDL design) n$ Z7 T: ~+ Q3 \2 \
1330580 SIP_LAYOUT SYMB_EDIT_APPMOD When adding a pin using the Symbol Editor the Pin Name is being changed if duplicated4 N% f2 M4 s) W4 O+ d5 F% P
1331028 CONCEPT_HDL CHECKPLUS Rules Checker fails on DE-HDL component.& P5 _) E( B7 }. Q
1331051 ALLEGRO_EDITOR INTERFACES Soldermask layer is mapped to both Soldermask solderPaste and Miscellaneous Image Layers columns using IPC-2581B
- _/ |6 O9 F1 [" e+ v9 X% v, E3 r1333127 CONCEPT_HDL CORE Sheet number in the new window is only the block-level number and not the design-level number
. w9 \( ?2 O0 X5 D1333591 SIP_LAYOUT SKILL Difference in behavior for padstack replace using axlPadstackReplace and command Replace Padstack+ F- \0 D; F- R' @4 e, b6 [
1333896 ASI_SI OTHER signoise -f and -k options don't work for net names with consecutive underscores.' l4 X9 W# f8 k% e. r
1333982 ALLEGRO_EDITOR ARTWORK ARTWORK: Coordinates of the hole get shifted by the "Draw holes only" option.' @9 @/ k3 M+ ^' D9 _& V! e y
1334302 CONSTRAINT_MGR SCHEM_FTB Import Logic - Import changes only or Overwrite current constraints fails to update signal models.
! ~) P$ ~5 {+ D0 ^1335276 CONCEPT_HDL OTHER On selecting objects near the schematic page border, the border is also selected9 C+ S3 g2 H4 J! @2 x; q
1336322 CONCEPT_HDL CORE DE-HDL does not open with maximized window.
; [5 _% n' f- g2 E- w5 q7 J1336783 PCB_LIBRARIAN IMPORT_EXPORT con2cap fails to export the part to OrCAD Capture format |
|
/1 
发表于 2014-11-16 10:30
收藏
淘帖
支持！
反对！
发表于 2014-11-16 23:52
