Cadence 16.6 Hotfix_SPB16.60.038

streetflower

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cadence 16.6 Hotfix_SPB16.60.038

7 o+ {) ~  T% |http://pan.baidu.com/s/1gdCb4cV
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! V" ?5 M7 h2 @4 P' h% \2 hDATE: 10-31-2014   HOTFIX VERSION: 038
' J7 y( U: v$ ?$ q& Y8 p- [===================================================================================================================================
3 R; |8 k: U- M5 yCCRID   PRODUCT        PRODUCTLEVEL2   TITLE
===================================================================================================================================
1103937 PCB_LIBRARIAN  VERIFICATION     con2con should not have any need for a graphical terminal
1107843 FSP            OTHER            Support for lRF and lmf in archived project
1123765 CAPTURE        GENERAL          .OLBlck file not deleted if library is closed in Capture
1169740 FSP            OTHER            Ability to import "Assigned Pin" column to connect Generic connector and FPGA.
1172641 FSP            FPGA_SUPPORT     Support for 5SGSMD5K2F40I2N device
) @4 r# _4 N1 m% S. m' x# o* W1177760 CAPTURE        OTHER            IC pins cannot be cross probed from Capture to PCB Editor
3 s9 @9 r3 p% w& f0 M2 I- K1195672 allegro_EDITOR PLACEMENT        Place replicate update should update component value text
+ p* x5 o! L: g* k! D0 Y2 S1206563 FSP            GUI              Spreadsheet import support for xc3s400afg400
& g$ i: g  _0 P  S1208169 FSP            FPGA_SUPPORT     New FPGA model request
1224428 ALLEGRO_EDITOR PLACEMENT        Get message "W-(SPMHGE-579): Unable to complete path to circuit for all selections" when updating place replicate circuit
! I4 s/ N! d# R6 O  A0 d1230064 ALLEGRO_EDITOR INTERACTIV       Place replicate is trying to match dimensions
8 w: S3 B4 t$ y) [% X# j& ^: D1253986 concept_HDL    CORE             Not able to define Source when adding property to a selected group
+ f7 D  e3 }4 T" R4 x, _) F1266615 ADW            SHOPINGCART      Error(SPDWUB-48) while placing the part from the shopping cart
" d$ X: e) E2 \) G1269658 ALLEGRO_EDITOR EDIT_ETCH        Ratsnest disappears near pin when routing
! e) H6 r# |; \: F& M9 x- i1270158 CONCEPT_HDL    CONSTRAINT_MGR   Orphan nets are visible in CM but not in DE-HDL
* A7 f) M! J5 M# H# v1275042 CONCEPT_HDL    COMP_BROWSER     Unit specifier 'HC' not found in UNITS environment while placing the part on schematic
1276269 ALLEGRO_EDITOR TESTPREP         On creating a fixture, a test point is generated but refs are not visible.
, D1 S( J$ C/ p* i" i! Q1278037 SIP_LAYOUT     ASSY_RULE_CHECK  DRC soldermask to finger check required for cases when the finger has no wire attached
" K) Q9 M: z0 o- l; }( O  p+ p5 [5 n1278475 ALLEGRO_EDITOR DATABASE         Import Logic changes VIA net names to GND
1279162 SIP_LAYOUT     DIE_ABSTRACT_IF  Add codesign die should default shrink/scribe settings from die abstract if abstract contains this information.
. c' A' q  o, n! o/ ^1282358 SIP_LAYOUT     OTHER            Why are IC/PKG symbols always mirrored when placed on a sip design?
1283439 CAPTURE        ANNOTATE         Inter Sheet Refs placed on top of Off Page Connector name
1284809 ALLEGRO_EDITOR INTERACTIV       Using the Fix icon in the toolbar will not apply the Fixed property to Groups
1286277 CAPTURE        SCHEMATICS       Capture crashes on adding Bezier curves
1286354 CONCEPT_HDL    CORE             The GENERATE_SCH_METADATA 'ON' directive causes significant DE-HDL performance degradation
' R" _/ F: Y* T6 C: D1286617 CONCEPT_HDL    CORE             Generate View failure
$ Q2 A- Y" o0 m- r1287020 CAPTURE        OTHER            Option to disable Autobackup
1287100 FSP            DESIGN_SETTINGS  FSP global edit of Capture library paths
4 S) o* M! u/ f: ?5 v( [1287877 CONCEPT_HDL    CHECKPLUS        Graphic check in CheckPlus hangs with sch_something view
- u( I* j& Y1 m1289056 ADW            OTHER            MKnet program to also read the alim.auto from ADW_CONF_ROOT
9 q9 z6 _/ z3 C; K' f1289107 CONCEPT_HDL    CORE             Find with Schematic Selection fails after clicking Find All three times
1289175 CAPTURE        OPTIONS          Autobackup changes timestamp of each and every part in the library.
1289447 TDA            CORE             Undo Check-out removes new design data from local area
8 B6 e) A% j2 M+ j; r9 S1289677 ALLEGRO_EDITOR SHAPE            Complex shape filling fails without DRC
1289755 ALLEGRO_EDITOR EDIT_ETCH        Timing Vision Display error
1289913 ALLEGRO_EDITOR EDIT_ETCH        Enhance the fanout function to speed up the layout design in Allegro PCB Editor.
1290136 ALLEGRO_EDITOR EDIT_ETCH        Unable to connect IC pin to ground
1290426 SIP_LAYOUT     LOGIC            Deleting a distributed codesign component from parts list does not remove the component information from the design database
: @" b6 H# q( J" {( k1291888 ALLEGRO_EDITOR INTERACTIV       Property DYN_DELETED_ISLAND is not added on all the voids created by Delete Island command
2 l5 V/ L: J& c! l1292206 ALLEGRO_EDITOR OTHER            Allow netname to be visible for pin/cline when viewed in Allegro PDF Publisher
$ _5 s; C5 i; M6 l3 |1292234 APD            SHAPE            Shape does not Void around Clines and Vias due to some corruption
: K! K7 H- {2 e! Z. w3 H$ I/ \1292877 ALLEGRO_EDITOR DATABASE         DB doctor fixed void boundary but deleted all boundary without detail information.
1293041 ADW            COMPONENT_BROWSE Component Browser does not show results if you filter on the PPL and an additional column
1293188 ALLEGRO_EDITOR EDIT_ETCH        fanout function(via in pad) deleted the cline & thermal
, A; D# @5 _, n! E1293626 CONCEPT_HDL    CORE             Delete Page command could not delete the dependency file (page2.csd).
1293710 ALLEGRO_EDITOR EDIT_ETCH        PCB Editor crashes during copy fanout
$ d, ]4 w: a$ [; [- j! g8 }1294355 Pspice         SIMULATOR        Function "ddt( )" behavior in DC sweep analysis
1295232 CAPTURE        SCHEMATIC_EDITOR Remove from group changes not reflected consistently in Part Manager
' m5 Y* c$ _$ y. j! S7 O, k1295434 ALLEGRO_EDITOR INTERACTIV       Enable Pin Name to be imported into a .BRD and display this in the show info output as done in APD and SIP
1296583 ALLEGRO_EDITOR FSP_PINSWAP      Crash for FSP Auto Pinswap with PCB Editor
1297095 ADW            LRM              LRM replaces incorrect part in schematic.
6 S) L. Z& \( V4 m9 b+ p+ F1297685 F2B            DESIGNVARI       'Could not open xmodules.dat file' Error during 'Save'.
* q* _# X" Q/ `5 u  M1297835 ALLEGRO_EDITOR INTERACTIV       DFA-Driven Interactive Placement not working correctly for components on bottom side
1297870 SIP_LAYOUT     ASSY_RULE_CHECK  Wire to Wire Optical short ADRC reports wrong DRC violation
' w8 g) b' F$ b7 g. i: h  R. ?: W( F: Z1297994 ALLEGRO_EDITOR INTERACTIV       When moving a via and splitting the stack, the via moves off the design work surface.
8 N1 e) @; H; u* S2 l0 b# m! @% U1298129 ALLEGRO_EDITOR EDIT_ETCH        Auto Interactive Phase tuning should have option to Allow DRCs
1299050 ADW            PCBCACHE         Need a way to turn off all project ptf file backup files under flatlib
6 x- n; e( @/ ~9 h1299873 CONCEPT_HDL    CORE             DE-HDL window size and position is not saved on exit
$ X+ ^8 m: y% D* s# s  N1 E* S) {1300101 ALLEGRO_EDITOR GRAPHICS         Inconsistency in symbol editor and PCB Editor while showing 3D view
1300557 ALLEGRO_EDITOR EDIT_ETCH        Move Component with "Slide Etch" or "Stretch Etch" removes DYN_CLEARANCE_OVERSIZE from clines
1300806 ALLEGRO_EDITOR GRAPHICS         Stroke command in 16.6 works differently as compared with earlier versions
1302103 CONCEPT_HDL    CONSTRAINT_MGR   DE-HDL CM startup time on large hierarchical is extremely large(6-8 min)
" ~5 ]5 d8 S9 q1302939 ALLEGRO_EDITOR PARTITION        Place replicate modules lost with design partition
1303078 CAPTURE        STABILITY        Capture crashes on View -- Status Bar with no design open
  `' m+ ^) u8 G9 a7 `0 g! E7 \1303106 ALLEGRO_EDITOR skill            Creating shape with SKILL script does not work on SPB16.5 and SPB16.6.
" l; Y& P$ M7 |3 |. A1303442 ALLEGRO_EDITOR EDIT_ETCH        auto-interactive convert corner function crashes PCB Editor
3 H( a( `* u% }) W1303921 ADW            COMPONENT_BROWSE Datasheets with spaces are not viewable in component browser
% I3 b5 H1 ]% H# c6 [) x1304042 APD            LOGIC            ERROR(SPMHUT-43):netin command is not working for .mcm.
1304725 ALLEGRO_EDITOR INTERACTIV       Value 0 in Allegro Text Setup not valid anymore
1304734 ALLEGRO_EDITOR pads_IN          PADS_IN does not follow the settings in the options file
3 f: a' |$ A0 L3 U1 a1304882 CONCEPT_HDL    CORE             Hierarchy Viewer jumps up to the top on File Save
1 [! {" }4 q9 X) v- _% s* F1305147 ALLEGRO_EDITOR MANUFACT         Auto silk result is unstable.
1306323 ALLEGRO_EDITOR INTERACTIV       Mirror command does not seem to work correctly.
1306468 ALLEGRO_EDITOR DATABASE         Dbdoctor Crash
1307277 SIP_LAYOUT     IMPORT_DATA      Wants BGA Text-In Wizard to maintain Pad layer set in the text file instead of defaulting to Bottom layer.
1307367 FSP            FPGA_SUPPORT     FSP user needs 5SGSMD5K3F40I3N/5SGSED6K3F40I3N in FPGA models.
1307478 ALLEGRO_EDITOR mentor           unable to do PADS Library translation.
+ z6 c" `  X  j7 U  O1307626 ALLEGRO_EDITOR INTERACTIV       Pick window is different for command and from GUI
& R8 v$ U: N* y, y& J! M$ B1307785 ASI_PI         GUI              Decap Configuration GUI does not update until you deselect then select GND
1308163 SIP_LAYOUT     ORBITIO_IF       Importing OrbitIO with multiple packages and XDA file into SIP layout results in incomplete data
  f  O- Y. R/ h- Q8 l1308289 SIP_LAYOUT     ORBITIO_IF       Import OrbitIO into existing SIP database fails. Testing an ECO type of design flow
, u# d' o5 I8 m7 A1309315 CAPTURE        ANNOTATE         Incremental annotation is not giving correct refdes in case of attached complex hierarchical design
1 ]8 N3 ]1 Z0 ?4 {' i% x1310614 CONCEPT_HDL    CORE             Part Manager creates bogus directory on linux system
1311184 CAPTURE        NETLIST_ALLEGRO  Incorrect warning for DEVICE property value in netlisting.
9 Z# P  Y8 u" i* a1311719 ALLEGRO_EDITOR INTERACTIV       Allegro Component will not place on the canvas
1311757 CONCEPT_HDL    CORE             Cannot change a property from instance level to non-instance level
1 h' _& a2 H# j4 w& j1311848 CONSTRAINT_MGR OTHER            PFE is adding a capacitor after creating PI CSet
1312553 CONCEPT_HDL    CORE             Customer could not add their net property after deleting it.
& k9 C0 c& x# T1313068 APD            DIE_ESCAPE       die escape gen: Cannot route from pad of Via Structure.
) J) N  f# w( J. T0 a3 o$ Q1313239 CONSTRAINT_MGR CONCEPT_HDL      Diff pair constraints disappear if xnet is created for them in Editor
1313850 ALLEGRO_EDITOR PLACEMENT        Place Replicate ignores fillet at pins
1314207 ALLEGRO_EDITOR OTHER            PCB Editor crash when rotating IPF data
1314467 ALLEGRO_EDITOR INTERACTIV       With high_speed option selected, PCB Editor crashes on move operation
+ x3 K5 |, S, c3 B+ ]1314921 ALLEGRO_EDITOR PLACEMENT        RATS are wrongly displayed.
# i; c1 Z& h" |  o( @# {1314973 CAPTURE        OTHER            Cannot cross-probe all pins from Capture
1316295 ALLEGRO_EDITOR OTHER            .brd extension is removed after running DB Doctor from PCB Editor Utilities.
7 F% f+ Q8 d3 [1316757 ALLEGRO_EDITOR DRC_CONSTR       Spacing constraint error on negative layer
1316959 ALLEGRO_EDITOR PARTITION        Exported soft boundary partition2 symbol still cannot move out of partition boundary
/ c! P7 |  T, z1317157 SIP_LAYOUT     DIE_STACK_EDITOR After moving the Dies to different layers a Wirebond has changed the connection from the pin to a shape.
5 C3 R" [' T' g7 h9 w0 V1317480 ALLEGRO_EDITOR SYMBOL           Allegro DB check "SPMHA1-247 Illegal mirror error"
1317614 ADW            COMPONENT_BROWSE Datasheet_Url is not opening the file browser correctly
+ K. S' n) a% X0 h1317876 APD            COLOR            APD crashes when executing Color Dialog for Nets
1320028 FSP            DE-HDL_SCHEMATIC Error (10002: Cannot find a ppt part that matches the instance properties
# l5 u+ I  E/ N/ W3 G0 d4 N# ~  M1320438 ALLEGRO_EDITOR GRAPHICS         Could not save DFA spreadsheet
; k# K! p* a3 f) S+ t& h( I. y# g1322600 CONCEPT_HDL    CONSTRAINT_MGR   Cannot extract xnet topology due to missing model even if the model is present
1323327 CONCEPT_HDL    CONSTRAINT_MGR   Deleting Ref Electrical CSet from Diff Pair removes it from a Matched Group in DE-HDL
9 E* l- r. Z1 Z8 S( M1 u7 [9 O1325230 CONCEPT_HDL    CORE             DE-HDL crashes once the design is loaded.
, K2 U$ o! y/ p* _, g0 A6 L' R: U1325644 F2B            PACKAGERXL       CDS_LOCATION/$PN not deleted from property file(dcf) backannotation warnings
; P, a& m7 R6 S, u" [1 n1325905 CONCEPT_HDL    CORE             Schematic page import causes re-sectioning of the pins.
1326163 SIP_LAYOUT     OTHER            SiP Layout - Void Adjacent Layer - Include option to ignore same net object when voiding
1326696 CONCEPT_HDL    CORE             Cannot get concepthdl -product to invoke with the high speed already available
; s. d, n1 G. M; B1327367 CONCEPT_HDL    CORE             Crash when saving after adding block pin
! z3 o5 n2 C$ x8 d1327569 ADW            LRM              LRM does not update the headers if the part number is also changed
$ f* S3 s! j0 f% y+ o& t  L  E1329271 ALLEGRO_EDITOR DRC_CONSTR       Multithreading DRC check is flagging a DRC on the TOP Layer for Route Keepout that has the property ?SHAPES_ALLOWED? ON.
& x* L8 W: K" d9 p1329587 CONCEPT_HDL    CORE             Using the GROUP command does NOT place all objects in the group back on grid
: [/ _6 H7 C5 q' ~1330913 CONCEPT_HDL    COMP_BROWSER     Empty value in PTF file
1332728 SIG_INTEGRITY  OTHER            Signal model assignment form returning SYNTAX ERROR on Linux 5.0 5.7 and 5.9 with hotfix s036 and s037.

nathon

打了这个补丁，生成的钻孔文件cam350不认识，怎么回事？

menghunabc

怎么感觉打了补丁 和没有打之前一样的呢？

menghunabc

更新了038的补丁 怎么还是004啊？

menghunabc

:'(:'(:'( 原理图开不了了

ann_wz

难道这个补丁有问题

kevin890505

打了已经一阵子了，表示这一版本把许多测试内容，变更为正式功能，进步很大，新的功能强势的很。cadence给人的感觉是，本软件的目标就是，软件极度智能，PCB难度大幅度降低，设计周期大幅度缩小。NB的软件不需要解释啊。

墨客的秋天

补丁有问题啊

wangxs_song

墨客的秋天 发表于 2014-11-16 20:04
. J: h2 z: S5 S$ c* b+ W, Q补丁有问题啊

大多情况都是自己的问题，只是还没有足够去发现和反省而已。  166的补丁每次都有新改进，智能程度也越来越高了......只是.......

waiwai788

已经安装了，目前没发现问题，不知道是我用的太简单了？呵呵支持

nathon

钻孔文件打不开我觉的是cam350的问题。有人用genesis吗？不知能否打开？https://www.eda365.com/thread-102901-1-1.html

sinfy

不错，支持，我也下一个

sinfy

正需要呢，谢谢了

streetflower

sinfy 发表于 2014-12-4 14:37
, @! _( s4 \  D2 N( [5 d) r+ L正需要呢，谢谢了

- D( y  N: S7 ^- r+ R2 h5 h% W9 G$ I去下最新的039
Hotfix_SPB16.60.039
# F# q, ~) f" l" qhttp://pan.baidu.com/s/1mg5McFQ