|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
http://pan.baidu.com/s/1kToiYV1
( K+ j+ \, q# y6 x3 G9 F
) J, L/ f5 R7 A$ c3 ~& \5 m) K, ]% G* b# `$ |
DATE: 08-22-2014 HOTFIX VERSION: 0348 l% G' M0 F* I, w5 y) v( v
===================================================================================================================================/ U! e- _2 p5 ~8 q0 f$ }' u: b
CCRID PRODUCT PRODUCTLEVEL2 TITLE
/ E2 Z* ~: j% G8 ^6 z: K) [' ~. a===================================================================================================================================8 R. f8 H, D: ^% t' R9 m
932528 concept_HDL OTHER Ability to handle reusemodule in soft reuse blocks.- P! ?( ~1 B% D/ i4 I
1137838 FSP GUI Ability to add notes to the canvas. G! f1 Z1 Z, g: `
1274382 allegro_EDITOR OTHER Retaining rats at the end of the clines or vias
4 W3 S$ R" g" J2 A1283575 FSP DE-HDL_SCHEMATIC Force Schegen to use symbols from released library
* ~6 C* `# A0 B1296331 CONCEPT_HDL COMP_BROWSER CSV export no longer works properly from Component Browser) r0 R, H" N" [% e9 Z0 m
1297855 F2B DESIGNSYNC ds -automode error
7 Q3 A8 V' X/ T) P* u/ q/ \5 X1298028 CONCEPT_HDL CREFER CreferHDL crashes$ N: I, o/ ?9 X! Z
1299607 SIG_INTEGRITY OTHER AutoModel should generate ESpice models for illegal values
5 z$ q- t7 {: u; ?) _1299609 CONCEPT_HDL OTHER AutoModel should make an ESpice model for a 3 pin Capacitor
. T) O& {1 b6 O, w3 w% @1302013 ALLEGRO_EDITOR EDIT_ETCH AiBT Crashes Allegro for nets having T points
" Z9 j( U& T" _! B1302209 SPIF OTHER Can't Export to Router and create a Specctra file.9 q1 G5 ^4 O. e2 ^1 o/ ?
1302242 F2B PACKAGERXL Packaging a hierarchical project does not create a full pstdmodeldat file
. J1 ]" `4 }4 A7 o8 \1302285 SCM CONN_SERVER DSCS-120: Failed to open file <filename.xcon> in write mode! }% Z3 f, g" O$ U/ J& Q h. L9 {
1302310 ALLEGRO_EDITOR INTERFACES Need way to have user defined license packages win over cadence products.! d* w P# i6 \7 o' h5 O W
1302638 F2B PACKAGERXL Function swaps are not backannotated into the schematic
1 n: I- M) B$ P. k/ h% U5 l# Y% A1303170 SIP_LAYOUT DIE_STACK_EDITOR Using Die Properties to move a die to the bottom side causes some entities to disacociate from the part
8 N8 y# |* J. A9 h8 w2 I1303214 CONCEPT_HDL CORE DEHDL crashes$ j1 v8 c; ~: H% s& c& [
1303219 ALLEGRO_EDITOR COLOR The user preference variable color_dlg_auto_apply changes the colors in the Display category
2 q( X' {' a. T1303685 CONCEPT_HDL CORE DEHDL crashes when I save page 3
, o; t( g- y8 w1303897 CONCEPT_HDL CORE Tool crashes intermittently when editing top-level schematic
% a/ Q; O' ^. B* p$ k! D5 h1304656 APD PLATING_BAR Add Plating Bar command convert the Clines having Arcs to 45 Degree segments& a7 N" s, y# j5 |, F/ d# l
1306467 CONCEPT_HDL CORE Concepthdl crashes during model assignmnt
" h, D! f5 K+ B
( }4 g2 q1 F! P7 X6 q+ N: k. [" L% }5 Z# e4 m( {% E9 O
功能上的更新了 color_dlg_auto_apply 应用；勾选了此项后；设置颜色时不需要点击应用按钮了；显示很直观哦# c0 e* W, U0 Z
大家来试试吧3 x) O8 }5 I$ f# q8 @2 I
不足之处就是出钻孔文件导入cam350时单位精度还是有问题的；特别是勾选了CAM350后比例更加有问题。$ M: N, w0 x+ ]3 m/ X2 j
|
|
/1 
发表于 2014-8-25 20:15
收藏
淘帖
支持！
反对！
楼主
