这段文字如何理解呢？为何会进入亚稳态？

mengzhuhao

这段文字如何理解呢？为何会进入亚稳态？

2 F. i8 w6 O$ i* N' FIf the asynchronous reset is released at or near the active clock edge of a flip-flop, the output of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.

mengzhuhao

The biggest problem with asynchronous resets is that they are asynchronous, both at the
0 A* ]8 f* S9 z, H9 \assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the
* G% z, S* F4 _: S& qissue. If the asynchronous reset is released at or near the active clock edge of a flip-flop, the
2 Z5 @* K# E" ~, \! M# Goutput of the flip-flop could go metastable and thus the reset state of the ASIC could be lost.
( o8 b, n3 [# ~! CAnother problem that an asynchronous reset can have, depending on its source, is spurious resets
5 C! Z6 V1 q: _, i8 A; z% adue to noise or glitches on the board or system reset. See section 8.0 for a possible solution to
reset glitches. If this is a real problem in a system, then one might think that using synchronous
% h9 k1 b% O9 p# f3 L! \7 qresets is the solution. A different but similar problem exists for synchronous resets if these
spurious reset pulses occur near a clock edge, the flip-flops can still go metastable (but this is
% ]8 x0 w. L2 e7 T9 _7 rtrue of any data input that violates setup requirements).