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本帖最后由 auto1860 于 2020-11-4 13:30 编辑
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+ k1 |2 h) `! U4 ?5 \链接：https://pan.baidu.com/s/1f4DTDBhhjcKz4On13yCxSg 2 L3 H6 M9 k1 L5 _+ D9 D- S
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Fixed CCRs: SPB 17.4 HF012
1 T* V" H5 v9 H3 B10-30-2020
7 V1 m# E6 C0 z! E4 _. J) i) ~+ b========================================================================================================================================================; ]$ i) V; P" t" v$ P" f: k/ j
CCRID Product ProductLevel2 Title
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- H' Z2 S Y: J6 H7 w2324284 ADV_PKG_ROUTER OTHER APR fails to route and does not use the BBVias.
$ \* ~# U* w. h! H2346605 ADW ADWSERVER Librarian license incorrectly checked out by data nodes during LiveBOM creation
6 `, D/ B6 g1 Q+ ^* V9 Y* Y2317952 allegro_EDITOR 3D_CANVAS Allegro 3D Canvas does not show STEP models placed on paste mask correctly3 ]. ^/ r- ]" i/ S! A+ [5 |
2192222 ALLEGRO_EDITOR DFM Allegro PCB Editor crashed during check 'Mask' with the setting of 'Via Partially Covered With Mask Opening'' R$ _% b$ z) ^
2197203 ALLEGRO_EDITOR DFM Wrong alert on Soldermask sliver checking
' A/ y8 Z% i+ h6 r+ v s/ Z2280806 ALLEGRO_EDITOR DFM Importing netlist results in error related to illegal subclass (SPMHNI-234)
$ \+ X% U) I7 p8 @7 M7 \2262559 ALLEGRO_EDITOR DRC_CONSTR Copper Features: Minimum Acid traps Angle gives false DRC
( A! @3 J2 G) |8 x2319385 ALLEGRO_EDITOR INTERACTIV Find by Query for Via structures is not working with Symbol field filter
, |; s) v E9 M3 k, c$ { |- J- q2279179 ALLEGRO_EDITOR PLOTTING File> Plot ignores the printer setup properties and always prints in Portrait format.
E: n4 {3 R( k- d; c! F2306419 ALLEGRO_EDITOR PLOTTING File -> Plot -> Properties only accepts 'Portrait' and not 'Landscape'
% t5 B5 b4 m4 [" `2333930 ALLEGRO_EDITOR PLOTTING The File> Plot always prints PCB in portrait6 w7 L; `; _: w7 _* l2 M
2327088 ALLEGRO_EDITOR SHAPE Design Sync gets a SAV file reported but there is no information about the cause of the problem in netrev.lst( X& [% t2 w4 u }, q* b; h- j) ?' t+ ~
2331947 ALLEGRO_EDITOR SHAPE When adding shape, pressing the 'Shift' key ends the process9 G: L7 @4 V Y2 h$ _( g
2339008 ALLEGRO_EDITOR STREAM_IF Stream import view layers give error
2 Y4 U3 ]5 X% P4 z e% h# S( ~2328322 APD DRC_CONSTRAIN Database getting corrupted during artwork creation even after running DBDoctor.) l8 U, g ~# H: n0 ^: A: J. L
2280535 APD REPORTS About the missing fillets report result: Ignore fillets not generated inside via regular pad area) @! P0 M2 R& ]% Y1 K+ ?; d
2323629 CAPTURE OTHER Product unusable with DSN file: Operations have significant delays and application stops responding
/ i7 V6 `4 A2 ~- b1 I" d- v& P2261147 CONSTRAINT_MGR ANALYSIS Setting "Mechanical drill hole to conductor spacing" does not flag DRC$ W" Z) P2 W7 m4 v/ ?7 o, Y
2330712 CONSTRAINT_MGR DATABASE Physical Constraints Set value cannot be modified
& D' z6 {6 \7 S& F* [2333755 CONSTRAINT_MGR SCHEM_FTB CM simplified out-of-sync pop-up form has clipped text
g3 l6 F# h% x! |6 X( w2235714 CONSTRAINT_MGR UI_FORMS Using the 'Change all design unit attributes...' pop-up menu option changes only the Min BB Via Gap value
. H' o, \2 ?2 ~4 ~+ n2 L5 a3 @: N2288109 CONSTRAINT_MGR UI_FORMS Column sort is not working for match group/ y2 u/ b$ V) h# `
2306092 CONSTRAINT_MGR UI_FORMS Display Constraints shows empty constraints in Constraint Manager
$ _% P' o1 ~+ G# K% s2332795 CONSTRAINT_MGR UI_FORMS CMGR Worksheet colums are not sorted as per the columns definitions
* m( K' }: v+ |! A8 j2326995 PCB_LIBRARIAN SYMBOL_EDITOR Graphics and pin number locations are incorrect
+ M) X0 R( S! R! ]/ g$ ]1 d2280766 Pspice MODELEDITOR Error while converting Verilog-A model
! {7 _4 Z U/ E) q% V7 h2285008 PSPICE MODELEDITOR Model Editor crashes if file name does not match with IBIS model file name
W0 D9 e& u' q5 P2 G+ R: U2346048 PULSE ADHOC Importing or File New Block as a designer working on a design that has been shared does not work
+ I% @. K# v( F4 S5 ~2346643 PULSE ADHOC System Capture crashes when adding a part
' @) H4 L$ a) V! I3 F2214054 PULSE UNIFIED_SEARC Unified Search does not honor operating system HTTP proxy settings8 c6 V6 h& i& W, r3 U! v4 @
2325635 PULSE UNIFIED_SEARC Errors in Unified Search (vista) using customer database
) r4 z2 B$ Y' Z2326089 PULSE UNIFIED_SEARC Unified search does not show EDM parts and gives error (SPPSUN-1)9 F- W+ ?( r1 W2 N6 q- {, D/ Z4 g; v
2329750 PULSE VERSION_ON_SA Live BOM data disappearing from migrated DE-HDL design with variants* Z9 n4 ~; z0 r" g, A; o( e
2319690 SIP_LAYOUT EDIT_ETCH Allegro SiP Layout XL - Auto-I Breakout Closest End excessive run time: Takes long time to complete
5 e7 T7 y& k" D6 A2320336 SIP_LAYOUT EDIT_ETCH Auto-Interactive Pin Swapping /Auto Breakout cannot route in design
4 S% c3 R" X5 M5 M2333679 SIP_LAYOUT INTERACTIVE Add Offset Via Angle Field
! y6 Y0 L4 |3 O# [/ ~8 m* E2344732 SYSTEM_CAPTURE DESIGN_CORRUP Page cannot be loaded because the design database is corrupt
* @4 E- K+ @- O; y. w2342258 SYSTEM_CAPTURE MISCELLANEOUS System Capture is impacting PCB Editor GUI Readability by Setting QT_SCALE_FACTOR
/ J' y+ n1 }4 r" Z+ \+ v$ v2337610 SYSTEM_CAPTURE PART_MANAGER System Capture crashes when updating a part with changed PACK_TYPE and Symbol+ U1 X# X; Z$ d, t! p) N$ v! o6 S
2341550 SYSTEM_CAPTURE VERSION_ON_SA Projects migrated from HotFix 002 to HotFix 010 have slow peRFormance( P% x" ]% ^9 h' t
2341591 SYSTEM_CAPTURE WIRING Moving wire segments still leaves odd pieces of wires
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发表于 2020-11-4 12:16
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发表于 2020-11-4 14:16
