求助-QUARTUS II版本：13.0编译程序出现的问题

XIAOXIAOYUWU

QUARTUS II版本：13.0
* o% j3 u  p5 I$ sFPGA型号：EP2C8Q208
2 Z! V# e$ u* p* @1 |在编译的过程中出现了如下的警告：
' u' c  L: k* B, }  w9 H5 ?（1）Critical Warning (332012): Synopsys Design Constraints File file not found: 'exp08_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'exp08_demo.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
3 t8 Q, Z; B5 Z2 [- OCritical Warning (332148): Timing requirements not met
/ ?  U1 D$ H( u/ U( YCritical Warning (332148): Timing requirements not met
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4 \% R1 n4 J% T4 D3 n" b（2）Warning (306006): Found 4 output pins without output pin load capacitance assignment
: _( h7 R5 H& G5 h+ Z) T+ D        Info (306007): Pin "Data_Out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
0 Y2 A9 w1 G2 C& y( v0 c        Info (306007): Pin "Data_Out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
0 k1 x; T" W% k2 n: I, f* G0 F        Info (306007): Pin "Data_Out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info (306007): Pin "Data_Out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
程序是黑金开发板提供的程序：PS2解码 ，仔细检查了下，程序没有问题。
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/ F' V6 j! y5 V! Z# @求助大侠，有没有什么好的方法来解决上述两个问题。。。谢谢

zgq800712

有种东西叫衣来伸手饭来张口

dspdesigner

这时说，你的电路没有时序约束文件。在13.0和之后的版本，软件都默认要求开发者提供时序约束文件，如果没有提供，就会给出 “332012” 警告。再者，如果没有提供，软件会自动按照1GHz的要求来进行编译，时序要求当然就达不到了，就会得到“332148”警告。后面几条警告，是说输出引脚没有分配电容负载

eda366_murphy

这个 E 文 说，要用 TimeQuest Timing Analyzer 去产生时序约束文件。没有这个，编译器无法工作