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签到天数: 12 天 [LV.3]偶尔看看II
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我最近在看中国电力出版社出版的FPGA嵌入式系统设计与开发指南这本书,下面的代码是本书的第第一章的第三段代码,我使用QII 11.0WEB版本无论如何无法正确编译,总是提示10559错误,请各位高手帮我看下问题所在,谢谢!
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1 r: l: f( J% c' Llibrary ieee;+ \ A6 C! m' t7 f$ B
use ieee.std_logic_1164.all;
+ u) _, p o D( {0 Ause ieee.std_logic_unsigned.all;
0 n c( N/ Z7 A6 m2 E! Qentity counter8bit is
. E# j7 N( ^3 x6 O' ? port(int ,reset,enable: in std_logic;count_out: out std_logic_vector(7 to 0));1 A2 [6 |1 h Q( \! o4 F
end counter8bit;+ ^! b5 d' \+ V/ f
architecture counter of counter8bit is+ Q2 @! O& s. i
signal count_in: std_logic_vector( 0 to 7);
% N' A) M9 m A; g3 W1 ]; g* R begin
7 R( A. `& w/ \7 Q5 Z; f2 ? m process(input,reset)( u7 X; I0 l+ @) P$ O% i
begin$ i7 s7 _9 R# [
wait until rising_edge(input);/ [- \) {. K d3 W6 u: n& m, O
if reset='1' then7 A2 C/ ?' q) P' B" x, N6 ]
count_in<=(others =>'0');* A0 H- ?0 N( ]0 N, ^0 }
elsif enable= '1' then
. Y9 \1 d/ T: J8 g if (count_in="11111110") then 0 C k5 t! z! p+ Z! V+ \9 N2 ?
count_in<="00000000";( Y$ w) f- d6 t2 U
else
0 m' v. P z# C) \. A- }; S count_in<=count_in+1;7 u6 \8 \1 K( S. m3 I
end if;
3 p0 |. C: x' b6 c+ N end if;& y0 M# @( k8 L4 D; [; y
end process;) s1 Z3 @# H& ~
end counter;0 w% v) r: j0 S, R: b- i9 ]
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lInfo: *******************************************************************
# j, L4 ]! s) g; ~* CInfo: Running Quartus II Create Symbol File' ~! E9 d% X. \. k8 j* w5 f3 Y
Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
' d+ q+ p- ? J; M. V/ _; H Info: Processing started: Wed Jul 24 14:43:41 2013 ^4 q. ^- T8 ~6 D# [: n( }
Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition1 q5 D7 m- m3 @8 V0 F$ t( ~
Info: Processing started: Wed Jul 24 14:43:41 2013! H( S7 ~; E. R9 D' R m
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off penlvji -c penlvji --generate_
' \. T) U) d* OError (10482): VHDL error at counter8bit.vhd(12): object "input" is used but not declared, a; e6 x1 d. S4 p$ W+ j
Error (10559): VHDL Subprogram Call error at counter8bit.vhd(12): actual for formal parameter "s" must be a "signal"
+ E5 Y7 L: E" Z4 ?' d: X) P$ ]$ @Error (10482): VHDL error at counter8bit.vhd(10): object "input" is used but not declared
# A6 Z4 Q- S; M* S& C0 l) c! D- NError: Quartus II Create Symbol File was unsuccessful. 3 errors, 0 warnings' S" J% O- ]6 U) H! Y _$ r$ N5 I
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