TA的每日心情 | 开心 2021-8-20 15:20 |
---|
签到天数: 12 天 [LV.3]偶尔看看II
|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
我最近在看中国电力出版社出版的FPGA嵌入式系统设计与开发指南这本书,下面的代码是本书的第第一章的第三段代码,我使用QII 11.0WEB版本无论如何无法正确编译,总是提示10559错误,请各位高手帮我看下问题所在,谢谢!. y% L1 e/ o/ z" [! }9 N( u
. P; L( ?$ p) d% ?# {$ G- {
: a7 `7 B, n: T) E3 \! U `library ieee;
+ d" s% i- E8 ^! N& c+ ` Y, cuse ieee.std_logic_1164.all;
" ~3 k0 s0 p3 M& ause ieee.std_logic_unsigned.all;
0 r' l* r) R9 s$ K* @0 sentity counter8bit is
% M0 J$ j- j6 u: ~ port(int ,reset,enable: in std_logic;count_out: out std_logic_vector(7 to 0));9 l! {* \6 C; j) M7 n+ O
end counter8bit;% V, O8 R; a$ [" V7 @ k
architecture counter of counter8bit is
7 P2 f* ]3 g" }0 C signal count_in: std_logic_vector( 0 to 7);, Z+ { h8 f- Q9 A
begin6 S$ \8 {" b- w2 m1 c: {; {5 _! @& x) X
process(input,reset)4 t- N* ^: r m& A2 Q4 K
begin6 i% g8 a' ]* M) Y$ N& Q, k
wait until rising_edge(input);* Q B* W: L$ u6 w& \* ]% a6 d
if reset='1' then
$ H% l7 b' d: v. p1 L/ S8 g( ? count_in<=(others =>'0');
; D3 [. C6 V2 e2 l. t elsif enable= '1' then 8 `" m. J0 j6 i) @& i
if (count_in="11111110") then
) G6 I: S2 S9 R3 |2 p count_in<="00000000";# U: t2 i; P1 a
else
4 {$ d+ q5 w5 m9 l5 A- s' u count_in<=count_in+1;6 D' |" w! Y i. R* G" w( b4 P
end if;& |5 S# S; t; A% [8 C& H
end if;
e5 z4 @) R6 C9 O% d end process;1 B8 i7 r% o- ~, F5 V
end counter;
8 Z" l" [7 r3 N- k 8 i* d3 p9 d+ b) Y$ n6 M t
9 M! n' O" q) J$ V& X% _- U9 m8 ]! I- f( x8 r
lInfo: *******************************************************************
! h. j& a! y! s8 _% B3 C5 _Info: Running Quartus II Create Symbol File4 w+ h% ]) t9 \; n* \! V
Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition( g& ?! X+ X) q
Info: Processing started: Wed Jul 24 14:43:41 2013
- P9 }: X" z# E; N( R Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition+ Q8 R0 u0 i7 N2 q" Z
Info: Processing started: Wed Jul 24 14:43:41 2013
8 R1 d4 W @( r$ U$ aInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off penlvji -c penlvji --generate_4 ^% v* X/ C9 h' P6 F0 m- j( x
Error (10482): VHDL error at counter8bit.vhd(12): object "input" is used but not declared9 R; s+ D" L7 P+ k2 B
Error (10559): VHDL Subprogram Call error at counter8bit.vhd(12): actual for formal parameter "s" must be a "signal"4 `$ k) B4 K# \3 H; t
Error (10482): VHDL error at counter8bit.vhd(10): object "input" is used but not declared
7 z/ B I! R7 n9 a L& t. @' B1 oError: Quartus II Create Symbol File was unsuccessful. 3 errors, 0 warnings8 g$ t* I. \2 I. @
|
|