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签到天数: 12 天 [LV.3]偶尔看看II
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我最近在看中国电力出版社出版的FPGA嵌入式系统设计与开发指南这本书,下面的代码是本书的第第一章的第三段代码,我使用QII 11.0WEB版本无论如何无法正确编译,总是提示10559错误,请各位高手帮我看下问题所在,谢谢!, y J3 M. @& H8 ?$ B, x+ |7 X+ ?
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7 M2 {- K, W# m0 h% n, dlibrary ieee;/ {9 g" O9 p& ]' i* W4 f
use ieee.std_logic_1164.all;
( q( D$ _# }7 N; s% {9 R4 Puse ieee.std_logic_unsigned.all;
( j; L7 B X+ }# {# [entity counter8bit is
; b! C4 C) |% m v8 L' \ port(int ,reset,enable: in std_logic;count_out: out std_logic_vector(7 to 0));; T5 b# W6 \: z8 g# i
end counter8bit;
( R( p! Q3 E- q4 E3 g architecture counter of counter8bit is/ t; d: W+ K4 Q; G
signal count_in: std_logic_vector( 0 to 7);. J6 \% W4 u6 g, K8 q0 j2 \6 b, Z) [
begin7 t: q0 C# ]) H: l' u
process(input,reset)
# h3 _ ^( R F' O7 a* B& D l begin# ^& t5 m' C, H3 v3 ?" b
wait until rising_edge(input);/ L' u m9 `! O4 O0 a. j: @- ^3 S* L
if reset='1' then
( v3 v; ]( d* Y0 M& M8 Q count_in<=(others =>'0');
' x P+ M2 J q' I' e! E! u0 Q elsif enable= '1' then
! r# _' N) q+ J. Y1 }9 t" X if (count_in="11111110") then 5 y0 r5 y/ Z8 r
count_in<="00000000";
# l F) G" G" s) A else( K- J$ e1 D' H% ]: z+ r
count_in<=count_in+1;2 d$ H. r7 u% r2 u
end if;5 K6 N: c$ y, Z: @9 ~. Z; o/ {
end if;
8 N2 m' u' o" z end process;
$ P- `! A- c: A end counter;
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& w. U: U: T/ D# e" m
+ o6 Q; h- O9 DlInfo: *******************************************************************& e2 a/ D' {. D( \! B2 r! Y! H
Info: Running Quartus II Create Symbol File
% {' l1 ?2 O+ q5 ~ Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
" C# y# V! @* @3 v+ K Info: Processing started: Wed Jul 24 14:43:41 20136 K9 {" c+ a1 G9 p% a2 c/ ?
Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition$ p+ D: z m$ l& V$ w8 y7 ^. B
Info: Processing started: Wed Jul 24 14:43:41 2013! e+ j `" l$ b2 \- }6 M7 @) T
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off penlvji -c penlvji --generate_. F: U5 O+ j" ^) M) m. a
Error (10482): VHDL error at counter8bit.vhd(12): object "input" is used but not declared
# ^! C, ]# {& W4 S8 nError (10559): VHDL Subprogram Call error at counter8bit.vhd(12): actual for formal parameter "s" must be a "signal"3 V5 ~) |: H! Y* i
Error (10482): VHDL error at counter8bit.vhd(10): object "input" is used but not declared z5 Y$ T) ^7 X7 o
Error: Quartus II Create Symbol File was unsuccessful. 3 errors, 0 warnings4 a( R3 Q1 e3 p& T' l R$ F
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