请帮我看下下面的代码错在什么地方，谢谢！

freeunix

我最近在看中国电力出版社出版的FPGA嵌入式系统设计与开发指南这本书，下面的代码是本书的第第一章的第三段代码，我使用QII 11.0WEB版本无论如何无法正确编译，总是提示10559错误，请各位高手帮我看下问题所在，谢谢！
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1 r: l: f( J% c' Llibrary ieee;
use ieee.std_logic_1164.all;
+ u) _, p  o  D( {0 Ause ieee.std_logic_unsigned.all;
0 n  c( N/ Z7 A6 m2 E! Qentity counter8bit is
. E# j7 N( ^3 x6 O' ?  port(int ,reset,enable: in std_logic;count_out: out std_logic_vector(7 to 0));
  end counter8bit;
    architecture counter of counter8bit is
         signal count_in: std_logic_vector( 0 to 7);
% N' A) M9 m  A; g3 W1 ]; g* R         begin
7 R( A. `& w/ \7 Q5 Z; f2 ?  m          process(input,reset)
             begin
                    wait until rising_edge(input);
                          if reset='1' then
                           count_in<=(others =>'0');
                                elsif enable= '1'  then
. Y9 \1 d/ T: J8 g                                  if (count_in="11111110")  then
                                    count_in<="00000000";
                                  else
0 m' v. P  z# C) \. A- }; S                                         count_in<=count_in+1;
                                  end if;
3 p0 |. C: x' b6 c+ N                         end if;
                         end process;
                         end counter;
                                         
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lInfo: *******************************************************************
# j, L4 ]! s) g; ~* CInfo: Running Quartus II Create Symbol File
        Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
' d+ q+ p- ?  J; M. V/ _; H        Info: Processing started: Wed Jul 24 14:43:41 2013
        Info: Version 11.0 Build 157 04/27/2011 SJ Web Edition
        Info: Processing started: Wed Jul 24 14:43:41 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off penlvji -c penlvji --generate_
' \. T) U) d* OError (10482): VHDL error at counter8bit.vhd(12): object "input" is used but not declared
Error (10559): VHDL Subprogram Call error at counter8bit.vhd(12): actual for formal parameter "s" must be a "signal"
+ E5 Y7 L: E" Z4 ?' d: X) P$ ]$ @Error (10482): VHDL error at counter8bit.vhd(10): object "input" is used but not declared
# A6 Z4 Q- S; M* S& C0 l) c! D- NError: Quartus II Create Symbol File was unsuccessful. 3 errors, 0 warnings
       

gusumurong

这个错误信息给的还不够明显？

freeunix

但是我看了line12,没找到错误啊

gusumurong

你的输入接口只有int ,reset,enable。"input"信号在哪里呢？

zgq800712

object "input" is used but not declared
3 c( U, ^( a  z; c9 d你先把这句话翻译了再说。