EE TO PADS 转换问题

xiesonny

我先是 AD的PCB  转换成 pads 再转换成EE文件，在EE中将线画好。
& g% i3 ?" V1 u1 q3 q* D* D然后用PADS，再导入EE画好的PCB，转换是成功，有提示转换问题，只有元件不见了，其它的还有。怎么解决！！！

$ ?& }. `! k  D: u$ R) |
1 u) R1 E8 R' T# {' h' I转换提示内容如下
% k/ t  i0 J1 |: Z. yExpedition to PADS Layout Design and Libraries Translator (Version 9.5) 01/08/13 13:54:53
2 Q7 f0 r; @7 Y6 `. g; h0 mCopyright (c) 2012 mentor Graphics Corp. - All rights reserved

" g, N2 w% p; B  q- T, Q------------------------------------------------------------
Input folder: D:\1\EE\PCB\EE.pcb
* a" [$ P* E% p3 JOutput folder: EE_pads_5.pcb

) _! E  p$ E, d8 b5 A1 V[I] Preparing data...
8 L- p# Z, F+ g  HOutput file: EE_pads_5.pcb
[I] Loading...
4 \$ U* `" k% j; K[I] Translating Expedition design files from 'C:\Users\ADMINI~1\AppData\Local\Temp\' to PADS Layout design file
[I] Reading Pad Stacks...
[I] Reading Cells...
[I] Reading Part Numbers...
[I] Reading Job Prefernces...
! _* n# x( H. y  ^. w8 v$ X[I] Reading Net Classes...
9 ]# ?6 Z( h6 A* E[I] Reading Net Properties...
# \, ~3 h3 n1 Y9 Z0 D/ {2 p[I] Reading Layout...
9 n0 i9 x! k) k4 K& y5 k0 r[I] Translating data...
  o$ m+ V- H4 V[W] All coincident Pad Entry rules are translated to Default Rules level
6 M' ~2 D, Y/ x' s& a# @5 x3 y[W] Discriminate Pad Entry rules found, and the rules were not translated.
[W] Route grid is not set. Primary part grid is used for setting design grid.
% h" E: s; c% Y+ U- G[W] Part type 'RES' is not found, and the component 'R6' was not translated.
[W] Part type 'RES' is not found, and the component 'R9' was not translated.
. e, K& y( c$ ]4 B; s0 l[W] Part type 'RES' is not found, and the component 'R10' was not translated.
[W] Part type 'RES' is not found, and the component 'R5' was not translated.
[W] Part type 'RES' is not found, and the component 'R8' was not translated.
[W] Part type 'RES' is not found, and the component 'R7' was not translated.
[W] Part type 'RES' is not found, and the component 'R4' was not translated.
; Z2 h: M- k# E4 H$ f: G% Q[W] Part type 'RES' is not found, and the component 'R3' was not translated.
[W] Part type 'RES' is not found, and the component 'R2' was not translated.
4 `/ D8 g; X) ]  Y# W6 W[W] Part type 'RES' is not found, and the component 'R1' was not translated.
[W] Route outlines are not supported, and was not translated.
* ?% d; x- z! `6 y8 X/ S# }[W] Pin name 'R7-1' has wrong format. The pin was not included into the net 'GND'.
[W] Pin name 'R6-1' has wrong format. The pin was not included into the net 'GND'.
[W] Pin name 'R8-1' has wrong format. The pin was not included into the net 'GND'.
+ n* k! _# r" g" V9 d) J[W] Pin name 'R9-1' has wrong format. The pin was not included into the net 'GND'.
[W] Pin name 'R10-1' has wrong format. The pin was not included into the net 'GND'.
; [3 c. @# u+ B[W] Net 'GND' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
[W] Pin name 'R1-1' has wrong format. The pin was not included into the net 'NETR1_1'.
[W] Pin name 'R6-2' has wrong format. The pin was not included into the net 'NETR1_1'.
# _1 z' j8 v9 t5 Z" z3 @* ]4 F[W] Net 'NETR1_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
[W] Pin name 'R2-1' has wrong format. The pin was not included into the net 'NETR2_1'.
2 `" W+ [* F% C( s+ r: u9 U[W] Pin name 'R7-2' has wrong format. The pin was not included into the net 'NETR2_1'.
[W] Net 'NETR2_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
# G6 o% l6 w+ G6 L1 l[W] Pin name 'R3-1' has wrong format. The pin was not included into the net 'NETR3_1'.
[W] Pin name 'R8-2' has wrong format. The pin was not included into the net 'NETR3_1'.
6 g8 i' v4 {  l, G# {1 y- G; K[W] Net 'NETR3_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
) O0 l# u* y1 T; ^$ w' ]$ U7 j[W] Pin name 'R4-1' has wrong format. The pin was not included into the net 'NETR4_1'.
# Z3 z% Z6 v' M+ Z% |* _5 u* j[W] Pin name 'R9-2' has wrong format. The pin was not included into the net 'NETR4_1'.
[W] Net 'NETR4_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
0 b1 v9 K4 z) j& p[W] Pin name 'R5-1' has wrong format. The pin was not included into the net 'NETR5_1'.
[W] Pin name 'R10-2' has wrong format. The pin was not included into the net 'NETR5_1'.
[W] Net 'NETR5_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
[W] Pin name 'R2-2' has wrong format. The pin was not included into the net 'VCC'.
[W] Pin name 'R1-2' has wrong format. The pin was not included into the net 'VCC'.
; @* p* g% Z! r5 M) l" b1 t[W] Pin name 'R3-2' has wrong format. The pin was not included into the net 'VCC'.
& y8 \0 D+ |/ r0 ]+ Z4 \0 B[W] Pin name 'R4-2' has wrong format. The pin was not included into the net 'VCC'.
; V/ w* P7 G9 C0 N6 Y[W] Pin name 'R5-2' has wrong format. The pin was not included into the net 'VCC'.
4 @$ t2 J+ ^5 d6 H* L' N* @[W] Net 'VCC' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
[I] Completed
, f  Q3 B7 E2 X5 l

dali618

为什么要转，你不是两个工具都会用么

xiesonny

dali618 发表于 2013-1-8 15:48
5 L& X* }& `. {5 Z6 k3 @为什么要转，你不是两个工具都会用么

5 a- y1 J; ]8 q+ I# C7 {
1 m9 e! T# k: `! |7 l. B! l2 ~有些工程，比如AD的，或者PADS的，工程可能已经做了一部分，或者修改比较多，想转入EE中再重新布线。完成后，再转回PADS或者AD中，为一个完整的工程。

v520

我在转换时遇到icdb出错 请问楼主是怎么设置的？、
$ U2 A- i. B$ v9 z) A

TOTO

把CES关闭再转试一试。

xiesonny

TOTO 发表于 2013-1-9 16:21
$ M: E/ @! w+ b  X) M- m把CES关闭再转试一试。

呵呵，如果EE不能转PADS，比如导入错误，那么关闭CES后，的确就可以导入了。这个方法我知道。
我想知道的是，PADS转EE的文件，如果开启CES后，是不能导入的，但关闭后，虽然能导入，但就如我所问的问题一样，没有元件封装的。其它的可以转换

TOTO

xiesonny 发表于 2013-1-9 19:36
7 q8 ~/ G) v' ~" O7 U6 B- d呵呵，如果EE不能转PADS，比如导入错误，那么关闭CES后，的确就可以导入了。这个方法我知道。
我想知道的 ...

软件之间的转换不可能十分完美，由于没有看到实际情况，不太清楚造成所述问题的原因所在，但目前的解决方法可以保留转换后工程的线，铜皮孔等需要的信息，拷贝到没有问题的PADS工程上.由于本人能力有限，不知道这样的方法是否可以帮助您解决问题

xiesonny

TOTO 发表于 2013-1-10 08:46
软件之间的转换不可能十分完美，由于没有看到实际情况，不太清楚造成所述问题的原因所在，但目前的解决方 ...

6 ~& @* Q3 Q1 l7 d9 m% |' X
! g$ |. q9 p3 h# O/ u呵呵，这样的解决方案貌似不好。
  D  c( l- y- j0 Y/ B8 o* x我说一下具体过程吧。

+ L/ e  j% @2 ]1，不管用什么软件生成网络表，或者用原生的DX， 然后在EE中做的PCB工程。基本可以完美导入PADS中。
! z- _& M/ @5 v# _) V2，如果你是AD转PADS转EE，或者PADS转EE，你再想从EE转回PADS，问题就来了，如果打开了CES，要关闭CES才能导入PADS,虽然能导入了，但是，元件却不见了，就像我顶楼所贴的提示内容差不多。

我想解决的是2过程。
6 h  z7 D7 r  h( h. \! I% F因为有些工程可能原来是AD的，或者PADS，这样可以在EE中布局布线，完成后，再导回PADS，这样就是一个完整的工程。

donyli

请问下，EE怎么转PADS？
谢谢！

YiXue

规则都导进去了吗？

Yuanlonglong

CES没打开，在PADS里面import出现iCDB无法打开的错误

blmld

xiesonny 发表于 2013-1-10 14:17
呵呵，这样的解决方案貌似不好。
3 i1 \. o, y$ m4 ^我说一下具体过程吧。

. |/ i1 g4 ?7 i1 V. Y0 G7 }请问器件丢失问题解决了吗？能分享下解决方案吗，我也想知道怎么解决器件丢失问题。谢谢！