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EE TO PADS 转换问题

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1#
发表于 2013-1-8 14:01 | 只看该作者 |只看大图 回帖奖励 |倒序浏览 |阅读模式

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我先是 AD的PCB  转换成 pads 再转换成EE文件,在EE中将线画好。& {$ X) B2 j! x0 t1 a! E
然后用PADS,再导入EE画好的PCB,转换是成功,有提示转换问题,只有元件不见了,其它的还有。怎么解决!!!

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转换提示内容如下
% q( }  `/ j+ {# S; ]0 L4 WExpedition to PADS Layout Design and Libraries Translator (Version 9.5) 01/08/13 13:54:53
" n( }2 r* E# b: f1 I! lCopyright (c) 2012 mentor Graphics Corp. - All rights reserved
. v. q" f) {1 w4 ]! [/ @
8 }: S8 N+ [, W7 ?! b3 B------------------------------------------------------------
8 D1 v( `! n3 C: ?" HInput folder: D:\1\EE\PCB\EE.pcb& e2 h( s5 z% T, G' L' [
Output folder: EE_pads_5.pcb
" y2 [) q& H7 w5 K* f9 y: Q& a, c4 m7 \) g- m. B4 Y( F7 x$ q. ~
[I] Preparing data...' f* u& R9 Y: f# v; ?9 P; {  }- g
Output file: EE_pads_5.pcb / o# O7 K  U0 H0 E
[I] Loading...
$ C; [$ @: \. F; F( U2 X[I] Translating Expedition design files from 'C:\Users\ADMINI~1\AppData\Local\Temp\' to PADS Layout design file
6 z% [( x+ f+ E[I] Reading Pad Stacks...
  q8 C& c: R& J: r4 {0 |[I] Reading Cells...# R% n5 M. m2 U  m7 f5 J% s' r
[I] Reading Part Numbers...6 r8 d$ z/ m% F) S6 _/ `9 h
[I] Reading Job Prefernces...
- p/ L8 }0 _. f2 l) a[I] Reading Net Classes...5 j  m3 y; E. A
[I] Reading Net Properties...! w# U: d0 w7 [, Y( s
[I] Reading Layout...
4 y$ k% `0 \: s8 a: j[I] Translating data...  B* X% B4 l# e8 O6 J5 x3 T! i
[W] All coincident Pad Entry rules are translated to Default Rules level
2 a- L' D! _, H! [* ]+ c+ e+ n[W] Discriminate Pad Entry rules found, and the rules were not translated.  q: i! _' O0 u6 N1 a* \0 f! d
[W] Route grid is not set. Primary part grid is used for setting design grid.( Y4 ]+ E4 Z1 G( g, Y/ Z: ]
[W] Part type 'RES' is not found, and the component 'R6' was not translated." R  f2 [. M7 T* u2 n! \, U& Z
[W] Part type 'RES' is not found, and the component 'R9' was not translated.5 e3 z8 J5 J" ~' }
[W] Part type 'RES' is not found, and the component 'R10' was not translated.
! D" P/ T% |% d# z2 p[W] Part type 'RES' is not found, and the component 'R5' was not translated.3 e! A9 c' _7 z, O2 j
[W] Part type 'RES' is not found, and the component 'R8' was not translated.9 M$ m! `4 t3 @- }
[W] Part type 'RES' is not found, and the component 'R7' was not translated.
* U. F9 b- s7 M4 [" Z( E[W] Part type 'RES' is not found, and the component 'R4' was not translated., b6 l6 C1 P, O4 W2 [  ?: f- Q
[W] Part type 'RES' is not found, and the component 'R3' was not translated.0 [! O: |. J' d* v3 z
[W] Part type 'RES' is not found, and the component 'R2' was not translated.5 m5 _5 e6 i5 J5 |: k$ R
[W] Part type 'RES' is not found, and the component 'R1' was not translated.1 \4 \/ x, ?. @" U; L" ^( F
[W] Route outlines are not supported, and was not translated.
: q* H0 O9 o0 H  [3 X7 V[W] Pin name 'R7-1' has wrong format. The pin was not included into the net 'GND'.2 J; K, @: Y% \3 G) F6 S
[W] Pin name 'R6-1' has wrong format. The pin was not included into the net 'GND'.
" e) ?0 \; u. j. e[W] Pin name 'R8-1' has wrong format. The pin was not included into the net 'GND'.
* w5 |1 ^. j' i5 t2 O* y# R- v" \[W] Pin name 'R9-1' has wrong format. The pin was not included into the net 'GND'.0 v8 }  M/ U% l! Y) T
[W] Pin name 'R10-1' has wrong format. The pin was not included into the net 'GND'.6 _0 A6 _$ I3 ~4 m4 m! ^+ O# y
[W] Net 'GND' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
: L7 q! E" I. w( W[W] Pin name 'R1-1' has wrong format. The pin was not included into the net 'NETR1_1'.8 k! ]  p. e6 P% H! k3 L; O
[W] Pin name 'R6-2' has wrong format. The pin was not included into the net 'NETR1_1'.
2 E0 z/ s/ C) z6 n7 p. L/ P[W] Net 'NETR1_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
8 h5 U: x) l2 E/ m: L/ i3 Y! P) n[W] Pin name 'R2-1' has wrong format. The pin was not included into the net 'NETR2_1'.; z- I2 q4 Z% o6 B2 I
[W] Pin name 'R7-2' has wrong format. The pin was not included into the net 'NETR2_1'.# H$ u  a& n3 W9 u- ~/ g2 V$ W
[W] Net 'NETR2_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
$ f) M! ~& ?# G[W] Pin name 'R3-1' has wrong format. The pin was not included into the net 'NETR3_1'.0 k5 G1 w6 C  T- W
[W] Pin name 'R8-2' has wrong format. The pin was not included into the net 'NETR3_1'.
* p% c' H4 N  s' z: g( P  k( i" E[W] Net 'NETR3_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
' H2 W& ]. E# _[W] Pin name 'R4-1' has wrong format. The pin was not included into the net 'NETR4_1'.
9 T% |5 n$ E( y% p  D# x& g% d[W] Pin name 'R9-2' has wrong format. The pin was not included into the net 'NETR4_1'.- F4 l6 _. }% e! x8 k1 i* D( K, c
[W] Net 'NETR4_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.; o7 H2 ]5 G# |8 u1 Q5 I
[W] Pin name 'R5-1' has wrong format. The pin was not included into the net 'NETR5_1'.7 R: n! w9 x( j, n3 k: H, c
[W] Pin name 'R10-2' has wrong format. The pin was not included into the net 'NETR5_1'.2 S- M3 H1 }3 Q3 i$ L+ I2 V+ B
[W] Net 'NETR5_1' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.; K/ }4 {) J# E" V' i5 k
[W] Pin name 'R2-2' has wrong format. The pin was not included into the net 'VCC'.
4 Z# P, c* v8 Z[W] Pin name 'R1-2' has wrong format. The pin was not included into the net 'VCC'.* ^$ ]" X9 O- `
[W] Pin name 'R3-2' has wrong format. The pin was not included into the net 'VCC'.' q0 B! b% Q) _7 C
[W] Pin name 'R4-2' has wrong format. The pin was not included into the net 'VCC'.
7 @, a; q8 F' F. b# C. g) X! Q/ W3 G[W] Pin name 'R5-2' has wrong format. The pin was not included into the net 'VCC'./ E0 ~% S" g. _
[W] Net 'VCC' don't have properly pin pair. Vias of the net were not translated and traces were translated to open coppers.
$ a7 H. H2 @- }8 ?; G0 z[I] Completed
  f, N, _6 y- J

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2#
发表于 2013-1-8 15:48 | 只看该作者
为什么要转,你不是两个工具都会用么

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3#
 楼主| 发表于 2013-1-8 17:17 | 只看该作者
本帖最后由 xiesonny 于 2013-1-8 17:58 编辑 1 C; {' i3 I( N- B1 Z5 {
dali618 发表于 2013-1-8 15:48
# k) K* j4 W9 j8 d- }7 m为什么要转,你不是两个工具都会用么
4 y- R6 w! A9 O9 C/ y3 q  _# n

7 |+ x; m8 J# R/ V: I6 Z有些工程,比如AD的,或者PADS的,工程可能已经做了一部分,或者修改比较多,想转入EE中再重新布线。完成后,再转回PADS或者AD中,为一个完整的工程。

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4#
发表于 2013-1-9 12:29 | 只看该作者
我在转换时遇到icdb出错 请问楼主是怎么设置的?、& L3 x; r' p! I8 M

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5#
发表于 2013-1-9 16:21 | 只看该作者
把CES关闭再转试一试。

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6#
 楼主| 发表于 2013-1-9 19:36 | 只看该作者
TOTO 发表于 2013-1-9 16:21 2 M& G' @/ h$ R/ e
把CES关闭再转试一试。

! t" ]# X, p' m呵呵,如果EE不能转PADS,比如导入错误,那么关闭CES后,的确就可以导入了。这个方法我知道。
  N, j! {7 d1 X+ k我想知道的是,PADS转EE的文件,如果开启CES后,是不能导入的,但关闭后,虽然能导入,但就如我所问的问题一样,没有元件封装的。其它的可以转换

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7#
发表于 2013-1-10 08:46 | 只看该作者
xiesonny 发表于 2013-1-9 19:36
- z! L/ B; t; L呵呵,如果EE不能转PADS,比如导入错误,那么关闭CES后,的确就可以导入了。这个方法我知道。
5 ]7 C4 F, H& I) K我想知道的 ...
# d, c! G, X$ T2 ]
软件之间的转换不可能十分完美,由于没有看到实际情况,不太清楚造成所述问题的原因所在,但目前的解决方法可以保留转换后工程的线,铜皮孔等需要的信息,拷贝到没有问题的PADS工程上.由于本人能力有限,不知道这样的方法是否可以帮助您解决问题

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8#
 楼主| 发表于 2013-1-10 14:17 | 只看该作者
TOTO 发表于 2013-1-10 08:46 4 h5 Z7 d5 C  s6 `) z2 P
软件之间的转换不可能十分完美,由于没有看到实际情况,不太清楚造成所述问题的原因所在,但目前的解决方 ...

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* ^2 d2 ~+ W( b! n* L1 Y呵呵,这样的解决方案貌似不好。2 e( B: x( }5 B$ M- @3 k, H! p
我说一下具体过程吧。
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% f  V$ k  T2 u3 x; p% G1,不管用什么软件生成网络表,或者用原生的DX, 然后在EE中做的PCB工程。基本可以完美导入PADS中。0 W3 i8 {1 S4 @- H  s  _% @% B
2,如果你是AD转PADS转EE,或者PADS转EE,你再想从EE转回PADS,问题就来了,如果打开了CES,要关闭CES才能导入PADS,虽然能导入了,但是,元件却不见了,就像我顶楼所贴的提示内容差不多。
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我想解决的是2过程。
1 N* }: S; m6 S: S9 T4 B! e因为有些工程可能原来是AD的,或者PADS,这样可以在EE中布局布线,完成后,再导回PADS,这样就是一个完整的工程。

点评

请问器件丢失问题解决了吗?能分享下解决方案吗,我也想知道怎么解决器件丢失问题。谢谢!  详情 回复 发表于 2023-2-21 10:53

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9#
发表于 2013-3-3 22:20 | 只看该作者
请问下,EE怎么转PADS?# C* T9 L0 t; ^/ F- t' t9 r
谢谢!

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10#
发表于 2013-11-12 16:01 | 只看该作者
规则都导进去了吗?

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11#
发表于 2014-12-9 16:01 | 只看该作者
CES没打开,在PADS里面import出现iCDB无法打开的错误
  • TA的每日心情

    2024-5-10 15:33
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    12#
    发表于 2023-2-21 10:53 | 只看该作者
    xiesonny 发表于 2013-1-10 14:17
    3 ]( w1 Y0 }0 w: [- _呵呵,这样的解决方案貌似不好。1 P/ m7 B6 t$ ?, O, n
    我说一下具体过程吧。

      ~/ f8 V  c- Y! f3 A  T+ D: v请问器件丢失问题解决了吗?能分享下解决方案吗,我也想知道怎么解决器件丢失问题。谢谢!/ n7 m1 m* Z8 v8 e7 x0 X2 ^
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