菜鸟求组:仿真multi-threshold cmos,实现NAND gate

ak11112222ak

source 总是出现以下问题，描述的时候已经说了是接地的了啊，为什么还是会当作断开的呢？
5 [$ F9 E, t2 }, S. S2 eCircuit: *Main mtcoms file

( g3 N4 `; `: L6 z) UWarning: There are nodes with less than 2 connections.
The table of nodes with less than 2 connections is generated after sourcing...



4 f7 H# R: T! {/ A  I  s2 X; F***warning***: the following singular supplies were terminated to 1 meg resistor

supply       node1            node2
vdd           vdd                  0
( q* U3 @4 D9 xv1           a                  0
) X6 l8 [1 Z3 t* T- ~v2           b                  0
. g3 o, S$ a- g4 c) k1 ]/ S( {2 Ev3           sl                  0


9 f2 U' l/ w' \, j1 o* _# i) AThe following nodes have less than 2 connections:
9 N, Z" e& Q. v1 m% o2 T( G( ^-------------------------------------------------------------------------------------
| sl                 | b                  | a                  | vdd                |
$ y  y2 \  t+ ^$ [* W: @-------------------------------------------------------------------------------------
一个描述netlist的文件：
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! l3 y- ~( h  t$ r  p& m" A$ w6 K: o* SPICE export by:  S-Edit 15.13
( s* t7 l6 m* C6 p* Export time:      Tue Jun 12 11:15:52 2012
/ y5 b# h, V  H5 a) Y  p2 U4 g* Design:           mtcoms
# H0 f7 n1 j' \% d* Cell:             Cell0
* InteRFace:        VResistor
7 Z& \. e! a, j: O. V* C! D* View:             VResistor
* View type:        connectivity
# S+ L; J9 n1 A  d4 ~! W6 ^3 ?* Export as:        top-level cell
, Z1 ]3 }5 a: [* m5 ?6 q7 s/ J* Export mode:      hierarchical
6 A% {) O2 x3 m/ {6 ]( c; p6 ^* Exclude empty cells: no
% i& k" Z3 c% |) P0 Y9 p* Exclude .model:   yes
3 k7 Q# K; x; q* S* Exclude .end:     no
* Exclude simulator commands:     no
) L% I* C5 N1 [2 I: ~8 Z* Expand paths:     yes
- e0 z' a9 u2 X8 K$ }* Wrap lines:       80 characters
* s: j2 R0 i6 m& Z. W* Root path:        \\en-file\users\houx\Profile\Desktop\ankun_dong hw2\mtcoms
* Exclude global pins:   no
4 o' Q+ }7 L2 [1 T: V% _* Exclude instance locations: no
. y, _6 R* y) q* Control property name: SPICE
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********* Simulation Settings - General Section *********
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*************** Subcircuits *****************
.subckt INV A Out Gnd Vdd  
7 `5 m- c+ r' K3 D
* k5 @+ T2 i) z2 [) {7 M*-------- Devices With SPICE.ORDER < 0.0  --------
* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
' I$ k# @* h  `- S& a  @* Organization: Tanner EDA - Tanner Research, Inc.
/ \+ H6 S% e! g! R. d* Info: Inverter
* Date: 06/13/07 16:17:11
- ^0 u* i1 n* h$ C5 ^5 [* Revision: 3 $ $x=7600 $y=600 $w=3600 $h=1200
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*-------- Devices With SPICE.ORDER > 0.0  --------
MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=4600 $y=2600
  u/ O$ Q3 \* r8 _% ~; Y+$w=400 $h=600
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=1.5625p PS=3.75u AD=2.25p PD=6.8u $
9 y) c! |% {, ?- H  r; w: B8 W. d, o+$x=4600 $y=3600 $w=400 $h=600
7 {3 l; Z' T6 g+ _3 L; k3 }6 ~7 d.ends



& Y6 r. w/ P5 S1 A2 S# A*-------- Devices With SPICE.ORDER == 0.0  --------
- G3 i0 ]% f+ B) }1 ^***** Top Level *****
XINV_1 SL N_2 Gnd Vdd INV $ $x=350 $y=-2300 $w=900 $h=600
2 a6 R5 \/ m' `+ T! c
*-------- Devices With SPICE.ORDER > 0.0  --------
: h+ R* U0 l* B- tCCapacitor_1 VDDV Gnd  1p $ $x=3100 $y=-400 $w=400 $h=600
4 P  a) r. e9 d8 e. vCCapacitor_2 GNDV Gnd  1p $ $x=3100 $y=-2500 $w=400 $h=600
9 n0 A- e) h$ F' T. A1 F  b* Y' RMNMOS_1 Out A N_1 N_1 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=-800 $w=400 $h=600
MNMOS_2 N_1 B GNDV GNDV NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
  G' a9 ]! ~% e, @) Z: c+$y=-1500 $w=400 $h=600
MNMOS_3 GNDV N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
  a1 Y# V3 X+ e. k. Z+$x=1100 $y=-2300 $w=400 $h=600
) m0 X9 n( V) qMPMOS_1 Out A VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=300
  U, X: X+ E# A; b1 R6 Q+$y=-200 $w=400 $h=600
1 Q0 A' f) i/ T5 m! T) r  Y* r4 QMPMOS_2 Out B VDDV VDDV PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1900
+$y=-200 $w=400 $h=600
& j" b9 G' d/ M6 aMPMOS_3 VDDV SL Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $ $x=1100
+$y=700 $w=400 $h=600

********* Simulation Settings - Analysis Section *********
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********* Simulation Settings - Additional SPICE Commands *********

.end
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icy88

source接地的描述应该是 vdd vdd 0 0,你后面少个电压的值