错误如下 - [( n" _5 G* c6 ~% x2 g# gERRORack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which * K. C% A. m- Z require the combination of the following symbols into a single SLICE : h v1 ?' }9 ~2 H component:3 [0 K* L* }/ B& J
FLOP symbol "Chain[37].uChain/Node[0].uNode0/uFdce" (Output Signal = 1 i! R$ Z& O4 a3 y$ K+ | Chain[37].uChain/wOutA0<0>) " v" Z0 a8 r0 N- o! \7 P FLOP symbol "Chain[37].uChain/Node[0].uNode1/uFdce" (Output Signal =; Z! M( U+ Z- Y5 f
Chain[37].uChain/wOutA1<0>) ( {1 Q4 o' C. ^' {8 l Z8 `' Z The set/reset signal Reset_IBUF_1 of register , U# N9 \$ R) n# t8 t Chain[37].uChain/Node[0].uNode1/uFdce doesn't match the existing usage of the5 G# f3 e; U+ {1 J( J. V
SR MUX. The signal Reset_IBUF_2 already uses SR. Please correct the design 7 ?% {9 D# s8 X; w/ b constraints accordingly.: B) |4 z; w2 y
请大侠帮忙
[复制链接]
/1 
发表于 2012-6-8 17:35
ack:679 - Unable to obey design constraints (LOC=CLB_R38C1.S0) which
收藏
淘帖
支持！
反对！