srio信号发送四组需要等长吗

ann_wz

srio信号发送四组需要等长吗 如题

超級狗

賽靈思（Xlinx）店煮蔬
- j5 I% ?' v' I$ u, g% ?High-Speed Serial I/O Made Simple
4 q- N2 F9 p( E1 f* C

fgjhtjbfem

魅族信号等长，等距就可以

派崔克林

如果是差分訊號就需要

弈点点电子

一般来说不需要

超級狗

7 B& ~; ~7 @9 `2 Y6 ?TI Application Note - Hardware Design Guide for KeyStone

! H5 N! G9 S7 Y4.3.2 SRIO Net Classes & Specific Rules
Routing requirements for the SRIO interface to the device shall adhere to good engineering practices for transmission lines operating above 6.25 GHz (actual operating frequency is 5 GHz). Specific attention shall be paid to net classes within this group and should have a high routing priority.
* e8 O# ^9 Q9 ?% ?5 s2 X0 M% f0 N

• Each complementary SRIO SerDes receive pair shall be individually skew matched to within 1 pS. 1 pS equates to approximately 5.464 mils to 7.092 mils (depending on propagation delays). Example of the SRIO complementary pairs include RIORXN0 & RIORXP0. All four complementary SRIO SerDes receive pairs shall be routed on the same layer.
• All four complementary transmit pairs shall be routed on the same layer.
• All four complementary receive pairs RIORXN/P3:0 shall be assigned and routed as an individual net class, routing skew shall not be greater than 15 ps between all receive pairs.
• All 4 complementary transmit pairs RIOTXN/P3:0 shall be assigned and routed as an individual net class, routing skew shall not be greater than 15 ps between all transmit pairs.
• Transmit and receive signals must be referenced to parallel ground planes.
• Vias are allowed and should never exceed 2 per complete net, all nets must be balanced and the impact of the via on timing and loading taken into account during design and layout.
• Differential signal routing must achieve a 100Ω differential impedance.
• If a SRIO switch is used, the specific routing and timing requirements shall also be incorporated.
  ) E+ {  O% D6 a# k2 O

" S+ o1 p6 g0 ~/ {/ }- k

超級狗

. G% k) |. ]6 S- b8 M6 r2 L. CTI Implementing Serial Rapid I/O PCB Layout on a TMS320TCI6482 Hardware Design

4.3.3 Interconnect
The geometry of the traces to link the transmitter and receiver ends is determined by the placement in the target system. Therefore, it is not possible to specify an exact layout for the interconnect. Instead, the trace may be placed as required, so long as it meets the following requirements:

• Edge-coupled, matched-length (±50 mils) differential pair.
• No stubs.
• No more than 30 inches (75cm) pin-to-pin, for 8-mil (.2mm) wide traces over FR4 material.
• 100 ohm differential impedance.
• No more than 3 sets of vias (not including via for BGA breakout on transmit end).
• Other signals are separated by at least 2x the differential spacing.
• Internal layers are strongly preferred. Avoid top and bottom layers.
• If connectors are used, they must be of a suitable 100 ohm differential-impedance, high-speed type, and count as 1” of trace for each connector pair.
• If cabling is used, it must be of a suitable controlled-impedance type (100 ohm differential or 50 ohm single ended), and counts as 1" of trace for each 1' of cable.
• If a mid bus probe is used, it must follow both TI’s and the probe manufacturer’s guidelines, and counts as 2” of trace.
  

" `8 ~, N# g& b6 J6 ~9 s

6940

进来看看，默默学习。
7 \5 H' A" M9 X" u, K: [

ann_wz

超級狗 发表于 2023-5-25 07:42
TI Application Note - Hardware Design Guide for KeyStone

2 t) N9 o: v* C9 R4.3.2 SRIO Net Classes & Specific Rules
...

感谢狗叔，意思就是组内延时差不能超过15ps，对不，洋文不太好
4 o# B7 }' U) Z3 w

超級狗

ann_wz 发表于 2023-5-25 10:06
感谢狗叔，意思就是组内延时差不能超过15ps，对不，洋文不太好

- e8 _3 s8 l% v( V9 R) ]+ W- \+ X第一篇講的是正負兩個訊號的等長建議。

第二篇講的是不同通道（Different Channel）間的等長建議。（+/-50mil）

我看哥的語意應該是想問第二個問題吧？
' B9 I# J% {- R+ S; Z5 }: D
# |7 p0 b. L7 e: j$ R4 }0 q8 ?
% G5 N* y1 \+ X" F& Z" U

ann_wz

超級狗 发表于 2023-5-25 10:11
) H2 W- _) d. A. G第一篇講的是正負兩個訊號的等長建議。

1 g% y- D. _' \) b- `7 }6 L2 W第二篇講的是不同通道（Different Channel）間的等長建議。（+ ...

$ j. Z- o* I" a  R  J7 V5 m感谢狗叔，，，，
1 z3 p# D' [3 c. Q1 X7 `