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orcad capture CIS16.3导出网络表的问题

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发表于 2012-3-31 11:28 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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我画好原理图后可以导出网络表,但是在PCB板时我想按页布置元件,所以在原理图中把每一页都加上一个属性PAGE,再来导网络表就报错ERROR:netlist failed.这是什么原因# I- ~1 N- L7 O2 B
session log0 Z9 l4 @  R# G1 \' W
Design Name:
4 k5 j$ C% b% yE:\orcad BACKUP\MYPROJ\myproj.dsn
3 B. y- E8 E! q) r5 N( CNetlist Directory:- P( g  u/ C1 C- A+ d! E
E:\ORCAD BACKUP\MYPROJ* |$ b- C7 ?5 l
Configuration File:
+ F. M: ~3 U  }  V' |" x- eE:\cadence\SPB_16.2\tools\capture\allegro.cfg
- i9 c, I* |: j4 I0 V
/ g% Q) o7 I1 O6 L5 W& Q( F; p- B" SSpawning... "E:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\ORCAD BACKUP\MYPROJ\myproj.dsn" -n "E:\ORCAD BACKUP\MYPROJ" -c "E:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"" o6 w1 q$ J/ U8 E8 ?; W* y! c
#1 Warning [ALG0051] Pin "GND" is renamed to "GND#1" after substituting illegal characters in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).
; |4 F9 ]/ @! d$ `#2 Warning [ALG0051] Pin "GND" is renamed to "GND#6" after substituting illegal characters in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).
/ w" r! T( z  T* N# E: }# e#3 Warning [ALG0016] Part Name "SW PUSHBUTTON-DPST_RESET_DSP-RESET" is renamed to "SW PUSHBUTTON-DPST_RESET_DSP-RE".
! }# n7 a3 F) A6 M7 @#4 Warning [ALG0016] Part Name "TMS320C6713GDP_BGA272DSP_TMS320C6713GDP" is renamed to "TMS320C6713GDP_BGA272DSP_TMS320".% ~$ y! M% e. j. t
#5 Error   [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.
* B" @- }( e  j3 }8 z              PAGE/ N  a1 i3 \( I: |, ^
#6 Error   [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.! ~. v$ Z# O1 s' h9 M2 a
              PAGE
% r- V8 Z1 @. ~: S* Y: i#7 Aborting Netlisting... Please correct the above errors and retry.
( Z' A1 Q! f8 x2 x8 x) }5 ~) x& D% k% V; @4 g( q+ `9 ~
Exiting... "E:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\ORCAD BACKUP\MYPROJ\myproj.dsn" -n "E:\ORCAD BACKUP\MYPROJ" -c "E:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"0 O! ~' E1 Z3 W6 ~' i* a3 \

0 i% r- p. Y7 g4 ~) k0 b, m5 j3 B+ \% P5 J7 |$ L0 n6 c- U$ R0 v7 }
*** Done ***
* U4 {+ X( d" r% ?0 l4 [7 B
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