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orcad capture CIS16.3导出网络表的问题

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发表于 2012-3-31 11:28 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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我画好原理图后可以导出网络表,但是在PCB板时我想按页布置元件,所以在原理图中把每一页都加上一个属性PAGE,再来导网络表就报错ERROR:netlist failed.这是什么原因
1 X/ K/ Z6 s: W% I) O3 M# g. R  nsession log% B+ n% T; F% B
Design Name:" C# w$ _% z  m% ^. Z
E:\orcad BACKUP\MYPROJ\myproj.dsn
+ {  X5 x% o& M) c  |: i" BNetlist Directory:  c3 t3 R8 R6 ^1 k+ u( x8 K% f" g% M
E:\ORCAD BACKUP\MYPROJ% j* W8 g/ R# k9 U* N! Z
Configuration File:
" s3 \1 l- C4 o" S0 G: }E:\cadence\SPB_16.2\tools\capture\allegro.cfg
; U! F7 k) M, P  M$ d6 N% E/ G2 {8 H6 V+ U) H8 l( h
Spawning... "E:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\ORCAD BACKUP\MYPROJ\myproj.dsn" -n "E:\ORCAD BACKUP\MYPROJ" -c "E:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint") p/ f4 e' O9 e' U( I& U
#1 Warning [ALG0051] Pin "GND" is renamed to "GND#1" after substituting illegal characters in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).
' R$ S# m% ?. H- T* k#2 Warning [ALG0051] Pin "GND" is renamed to "GND#6" after substituting illegal characters in Package AUDIO_RJ , J6: SCHEMATIC1, OPA_BUF (360.68, 53.34).+ q9 h& A3 v- }1 s9 G
#3 Warning [ALG0016] Part Name "SW PUSHBUTTON-DPST_RESET_DSP-RESET" is renamed to "SW PUSHBUTTON-DPST_RESET_DSP-RE".
9 E: _! A# h) L/ m& Y: t#4 Warning [ALG0016] Part Name "TMS320C6713GDP_BGA272DSP_TMS320C6713GDP" is renamed to "TMS320C6713GDP_BGA272DSP_TMS320".& _0 o* d- }0 n0 a: u8 N
#5 Error   [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.% d% d% d( `1 N6 a. f0 D: |8 b
              PAGE
9 U* O: R% J3 M; N* S6 B#6 Error   [ALG0013] Conflicting values of following Component Instance properties found on different sections of U6.
/ {  ^6 K1 w2 P2 e, _  X              PAGE8 A7 l# [4 v4 I6 ?6 {7 A1 d
#7 Aborting Netlisting... Please correct the above errors and retry.6 V5 {0 L" F8 X/ B" W) k

% o0 U. Y9 g; c! y" e& }8 @/ uExiting... "E:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\ORCAD BACKUP\MYPROJ\myproj.dsn" -n "E:\ORCAD BACKUP\MYPROJ" -c "E:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
5 P6 d' Q( x+ f5 C, `: m9 A7 g- C: {/ C" D' ]% e: w

/ a1 b: U) |! r$ r# |) {* S8 e5 P*** Done **** H" E: ]) @4 \( O  p7 Z& Z; l
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