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各位大神,小弟新使用MSP430F6726A做开发,遇到晶振不起振问题,头疼不已,还请各位大神指点迷津。6 s* V- g. e3 r/ k, t. d; Q: y( w
主要问题:使用32.768kHz晶振接mcu24,25管脚(XIN,XOUT),根据规格书使用12pF的匹配电容,晶振不起振,更换3pF,6pF,9pF,15pF,22pF,30pF,47pF匹配电容还是不起振,询问ti技术人员也没给出具体解决办法,基本上也是从PCB布线,电容匹配方面给分析的,但都已试过,没起作用,由于此款MCU自带晶振,外部晶振不起振会转到内部晶振起振,以下是源码部分从TI官网上弄得:% l) f! C/ z. t \4 j6 R1 a" o% m8 ]
void Systerm_Clock_init(void)
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1 S- b; H2 X& t& \ volatile unsigned int i;
% Y! m* ]3 j. h$ [9 a' O: s PJDIR |= BIT0 | BIT1 | BIT3; //ACLK, MCLK, SMCLK set out to pins8 {- h: Q& e9 @9 m
PJSEL |= BIT0 | BIT1 | BIT3; //PJ.0,1,3 for debugging purposes.
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& S% L9 }6 b3 [* I // Setup UCS ( C# f1 C: @5 ^, d% v
// Loop until XT1 fault flag is cleared
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) a3 e/ `, ^! v3 [- b" K' c9 g UCSCTL7 &= ~XT1LFOFFG; //Clear XT1 fault flags
) }& D2 f: {* z6 n, B; w3 A0 G8 Y) W3 j! d } while (UCSCTL7 & XT1LFOFFG); //Test XT1 fault flag
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' K |9 m, q/ Q) r! E$ `, O( F' M7 } UCSCTL6 &= ~(XT1OFF); //XT1 On
3 ^9 B5 w: B& `- H. u* s, n UCSCTL6 |= XCAP_3; //Internal load cap
% l. }' I, h/ `5 J& p2 N# H- D __bic_SR_register(SCG0); // Enable the FLL control loop
! `6 A2 S8 u |7 A. ^& |# _ UCSCTL0 = 0x0000; //Set lowest possible DCOx, MODx" s T" j5 v0 F7 c4 ]; J& G
UCSCTL1 = DCORSEL_5; //Select DCO range 16MHz operation
; m" J3 g4 l! p& A' B6 @' M3 b UCSCTL2 = FLLD_0 + 511; //(N + 1) * FLLRef = Fdco=(487 + 1) * 32768 =15990784Hz= 16MHz
. [! Z, p( t4 a$ } __bic_SR_register(SCG0); //Enable the FLL control loop
; Q* E1 u$ w) V. u' } __delay_cycles(600000); //32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
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UCSCTL4 |= SELA_0+SELS_3+SELM_3; //Set ACLK = XT1,SCLK=MCLK=DCOCLK=16M: @% I7 E8 S5 s4 j
UCSCTL6 &= ~(XT1DRIVE_3); //XT1 stable, reduce drive strength*/1 W0 n) F F( [
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}
+ Q" X8 N: o" j+ e% G实在不清楚到底哪出问题了,还望使用过此芯片的大神给指导一二。- h7 M% {( V- ^
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