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各位大神,小弟新使用MSP430F6726A做开发,遇到晶振不起振问题,头疼不已,还请各位大神指点迷津。
+ r: B7 ]) ?/ q8 W主要问题:使用32.768kHz晶振接mcu24,25管脚(XIN,XOUT),根据规格书使用12pF的匹配电容,晶振不起振,更换3pF,6pF,9pF,15pF,22pF,30pF,47pF匹配电容还是不起振,询问ti技术人员也没给出具体解决办法,基本上也是从PCB布线,电容匹配方面给分析的,但都已试过,没起作用,由于此款MCU自带晶振,外部晶振不起振会转到内部晶振起振,以下是源码部分从TI官网上弄得:. G- m- E! i# F6 V+ n# r
void Systerm_Clock_init(void)0 h# w- R' e: A7 Q
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volatile unsigned int i;
8 ^' J2 s4 @3 I2 i9 e* m PJDIR |= BIT0 | BIT1 | BIT3; //ACLK, MCLK, SMCLK set out to pins
- i6 Q- @) \: F' ~* ?) o; B- L8 G; B PJSEL |= BIT0 | BIT1 | BIT3; //PJ.0,1,3 for debugging purposes.$ ^2 F: H$ L+ X$ K# m& J9 x+ h
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2 B( ?2 K1 [3 \ // Setup UCS
! T+ C4 j1 q' q1 m& Z6 T // Loop until XT1 fault flag is cleared
/ F5 Y0 d+ |9 H8 h3 r& v/ L3 k do
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3 Y0 y1 @/ ^, }9 t1 f. @% D+ M UCSCTL7 &= ~XT1LFOFFG; //Clear XT1 fault flags
4 [6 J9 ~0 l& i% W# \9 B } while (UCSCTL7 & XT1LFOFFG); //Test XT1 fault flag: P& `+ ] |% A! f# a
' O; w6 ]* Y. N" ~. i4 y9 i UCSCTL6 &= ~(XT1OFF); //XT1 On
" [3 ?9 |# _& r4 h# l UCSCTL6 |= XCAP_3; //Internal load cap
8 r" z; {* o2 U- I% ]! h+ g __bic_SR_register(SCG0); // Enable the FLL control loop
& K$ K3 { a6 f; u. v: @/ ` UCSCTL0 = 0x0000; //Set lowest possible DCOx, MODx( \0 S" @+ l* F W! [! G5 r- w
UCSCTL1 = DCORSEL_5; //Select DCO range 16MHz operation
, x3 O" O# R! D9 u! C; I9 b UCSCTL2 = FLLD_0 + 511; //(N + 1) * FLLRef = Fdco=(487 + 1) * 32768 =15990784Hz= 16MHz # A4 M8 \+ E. z; v* \7 m5 M1 J% T
__bic_SR_register(SCG0); //Enable the FLL control loop# g6 _( X% S6 }1 G* L$ T
__delay_cycles(600000); //32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle5 E" U- S! R+ a$ e- V
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UCSCTL4 |= SELA_0+SELS_3+SELM_3; //Set ACLK = XT1,SCLK=MCLK=DCOCLK=16M
5 `$ c+ C% t% b1 \3 h. U- ] UCSCTL6 &= ~(XT1DRIVE_3); //XT1 stable, reduce drive strength*/3 Z/ j& r/ u5 E& x3 m) m/ u, i
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实在不清楚到底哪出问题了,还望使用过此芯片的大神给指导一二。+ h j% F s* @0 \
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