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各位大神,小弟新使用MSP430F6726A做开发,遇到晶振不起振问题,头疼不已,还请各位大神指点迷津。( U! z* H. E2 {
主要问题:使用32.768kHz晶振接mcu24,25管脚(XIN,XOUT),根据规格书使用12pF的匹配电容,晶振不起振,更换3pF,6pF,9pF,15pF,22pF,30pF,47pF匹配电容还是不起振,询问ti技术人员也没给出具体解决办法,基本上也是从PCB布线,电容匹配方面给分析的,但都已试过,没起作用,由于此款MCU自带晶振,外部晶振不起振会转到内部晶振起振,以下是源码部分从TI官网上弄得:+ S: J' v1 e2 W8 j! S7 Z
void Systerm_Clock_init(void)
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- `% \$ K8 O/ r- L- v. Z. S volatile unsigned int i; " k0 G& A7 h2 ^' S, `4 p
PJDIR |= BIT0 | BIT1 | BIT3; //ACLK, MCLK, SMCLK set out to pins4 x; q& e% \" X1 d5 G' L" H
PJSEL |= BIT0 | BIT1 | BIT3; //PJ.0,1,3 for debugging purposes.
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// Setup UCS 9 p, o7 ]0 C( k( I- e
// Loop until XT1 fault flag is cleared
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UCSCTL7 &= ~XT1LFOFFG; //Clear XT1 fault flags2 b* G+ X4 l) g4 Q9 ~1 G _4 V
} while (UCSCTL7 & XT1LFOFFG); //Test XT1 fault flag5 D) c& g3 ^- F( G, x% J0 O
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UCSCTL6 &= ~(XT1OFF); //XT1 On
% f4 E% T) a s6 n8 {4 q UCSCTL6 |= XCAP_3; //Internal load cap
X' g! m$ i3 \! B __bic_SR_register(SCG0); // Enable the FLL control loop0 ]( X3 F, t" y- e% T
UCSCTL0 = 0x0000; //Set lowest possible DCOx, MODx
7 a+ U9 b1 j! X) T4 {: `, [' Q. g/ |% d UCSCTL1 = DCORSEL_5; //Select DCO range 16MHz operation/ a2 c' Q z& G/ a. S6 Y: H
UCSCTL2 = FLLD_0 + 511; //(N + 1) * FLLRef = Fdco=(487 + 1) * 32768 =15990784Hz= 16MHz
5 [1 h- p! w, o/ F v1 X( } __bic_SR_register(SCG0); //Enable the FLL control loop) _/ I5 ~& ]/ J6 {/ B6 c( [6 e
__delay_cycles(600000); //32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle5 S1 }, P2 }+ k0 e9 @* w
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UCSCTL4 |= SELA_0+SELS_3+SELM_3; //Set ACLK = XT1,SCLK=MCLK=DCOCLK=16M
. v0 {4 }, r- N; m, v( V% Q UCSCTL6 &= ~(XT1DRIVE_3); //XT1 stable, reduce drive strength*// r2 y) {8 ]2 V+ c% K
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. _) c# l+ ^* G. q实在不清楚到底哪出问题了,还望使用过此芯片的大神给指导一二。! n7 O* R% m. L& I
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