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各位大神,小弟新使用MSP430F6726A做开发,遇到晶振不起振问题,头疼不已,还请各位大神指点迷津。6 q6 ^$ I+ f" ^$ E+ g
主要问题:使用32.768kHz晶振接mcu24,25管脚(XIN,XOUT),根据规格书使用12pF的匹配电容,晶振不起振,更换3pF,6pF,9pF,15pF,22pF,30pF,47pF匹配电容还是不起振,询问ti技术人员也没给出具体解决办法,基本上也是从PCB布线,电容匹配方面给分析的,但都已试过,没起作用,由于此款MCU自带晶振,外部晶振不起振会转到内部晶振起振,以下是源码部分从TI官网上弄得:, ~. W3 W/ x$ ]9 \" K
void Systerm_Clock_init(void)
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volatile unsigned int i;
2 x# M ^; F8 S( C PJDIR |= BIT0 | BIT1 | BIT3; //ACLK, MCLK, SMCLK set out to pins
- T7 Q' P2 @( p1 H5 C' I PJSEL |= BIT0 | BIT1 | BIT3; //PJ.0,1,3 for debugging purposes.; e: ~% T, T. o3 b! L+ _
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// Setup UCS
6 Q2 |7 h$ i, v/ @6 a // Loop until XT1 fault flag is cleared
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2 U# ^: }3 q. B+ e+ j$ Z- S i UCSCTL7 &= ~XT1LFOFFG; //Clear XT1 fault flags
$ a# G+ {3 n& ~0 ~: H7 Z } while (UCSCTL7 & XT1LFOFFG); //Test XT1 fault flag. {% W( ]8 o9 q- w
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UCSCTL6 &= ~(XT1OFF); //XT1 On
& ^) r- ~ ]: w' C ~7 Q) H UCSCTL6 |= XCAP_3; //Internal load cap
5 O9 J E6 c% l1 H7 J4 Q5 j __bic_SR_register(SCG0); // Enable the FLL control loop
5 Y: E+ b) |/ Q$ ? UCSCTL0 = 0x0000; //Set lowest possible DCOx, MODx
8 t7 w3 i& l0 B$ c0 k7 ~" ~4 c UCSCTL1 = DCORSEL_5; //Select DCO range 16MHz operation, }4 t6 Z+ H- _7 M
UCSCTL2 = FLLD_0 + 511; //(N + 1) * FLLRef = Fdco=(487 + 1) * 32768 =15990784Hz= 16MHz 2 w" P$ k: w; }/ d( V
__bic_SR_register(SCG0); //Enable the FLL control loop2 x2 ^( t% M& h$ y/ i3 \
__delay_cycles(600000); //32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle
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; a8 l8 i B/ A UCSCTL4 |= SELA_0+SELS_3+SELM_3; //Set ACLK = XT1,SCLK=MCLK=DCOCLK=16M
* d- [* r* ^; w0 \% U UCSCTL6 &= ~(XT1DRIVE_3); //XT1 stable, reduce drive strength*/5 O5 |. f" S8 s& D& z
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}
0 F; t7 U3 ` ^实在不清楚到底哪出问题了,还望使用过此芯片的大神给指导一二。2 P) B! J4 Z( \9 Y0 w' Z7 d
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