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Checking Schematic: FPGA
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Checking Electrical Rules
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# w8 b+ z: a4 D" w2 nWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_V21 Bidirectional Connected to Output Port: FPGA, PAGE-A1 DR FPGA END (4.90, 2.20)
, ]: M' x7 U, WWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AA19 Bidirectional Connected to Output Port: FPGA, PAGE-A1 DR FPGA END (5.00, 4.80)
2 W( _4 |6 }$ p, x' [WARNING [DRC0004] Possible pin type conflictWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_W15 Bidirectional Connected to Output Port: FPGA, PAGE-A1 DR FPGA END (2.50, 5.30) U1,IO_VB7N0_Y14 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (2.50, 5.50)
: p3 m4 `' D- ]8 l; hWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_V20 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.10)
+ ^ P7 m2 @/ r' \* C# `( LWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_V22 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.30)
; u3 A) s( s. q% D+ pWARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_W22 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.70)
: e3 I* Z0 [7 G2 v+ n7 bWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_W16 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (2.50, 5.40)
( n' J8 f% k( _6 {0 I; c5 iWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AB18 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (5.00, 5.60) ' h1 L6 s# @( s2 l
WARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_Y17 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (2.50, 5.60) / e. k( W! P; k* Y
WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_Y21 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 3.10) * {$ W+ a& d3 q4 j5 O
WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_Y22 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 3.20) $ E# W2 B3 |) ^% g9 O- z; D
WARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AA18 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (5.00, 4.70) ( C9 j- F$ Z9 @" Z
WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_W21 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 2.60)
! e( j, I0 @ Q$ `5 P2 MWARNING [DRC0004] Possible pin type conflict U1,IO_VB7N0_AB19 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (5.00, 5.70) ' y$ m1 F' s5 a. a$ d" E5 y) ]: F
WARNING [DRC0004] Possible pin type conflict U1,IO_VB6N1_R17 Bidirectional Connected to Output Port: FPGA, PAGE-A1:DDR FPGA END (4.90, 1.70)
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