cpld/fpga RTL和门级Modelsim仿真不一致问题

itch · 发表于 2022-7-11 16:17

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module PWM( clk,//系统时钟
rst_n,//复位
cs,//DSP片选
fault_and_out,//故障
overcurrent,//过流,逐波限流
ePWM_sync,//同步，即EPWM时基起始计时点
pwm1,pwm2,pwm3,pwm4,//PWM输入 pwm1_out,pwm2_out,pwm3_out,pwm4_out//PWM输出
);
input clk;//系统时钟 30M
input rst_n;//复位低电平有效
input cs,fault_and_out,ePWM_sync;//同步片选严重故障信号
input overcurrent;//过流
input pwm1,pwm2,pwm3,pwm4;//PWM输入
output pwm1_out,pwm2_out,pwm3_out,pwm4_out;//PWM输出
reg pwm1_out,pwm2_out,pwm3_out,pwm4_out;

parameter CLOSE_ALL=4'b0001,//关闭4个管子独热键编码状态机
CLOSE_OUTSIDE=4'b0010,//关闭外侧2个管子
//SET_INSIDE=6'b000100,//内侧2个管子强制导通全置1,1字型备用
OPEN_INSIDE=4'b0100,//打开内侧2个管子
OPEN_ALL=4'b1000;//打开内外侧4个管子，正常工作状态
reg[3:0] state;//状态机
reg[5:0] cnt_close;
reg[5:0] cnt_open;
//reg[5:0] cnt_set; //1字型备用
always @(posedge clk or negedge rst_n )//
begin
if(!rst_n) //复位
begin
{pwm1_out,pwm2_out,pwm3_out,pwm4_out}<=4'd0;//关闭管子
cnt_close<=6'd0;
cnt_open<=6'd0;
state<=CLOSE_ALL;
end
else
begin
case(state)
CLOSE_ALL:
begin
{pwm1_out,pwm2_out,pwm3_out,pwm4_out}<=4'd0;//初始化状态，关闭管子
if(!cs && fault_and_out && overcurrent && ePWM_sync) state<=OPEN_INSIDE;//等待片选选中且无故障进入下一状态
end
OPEN_INSIDE://打开内侧2个管子
begin
{pwm2_out,pwm3_out}<={pwm2,pwm3};//打开内侧2个管子2us
{pwm1_out,pwm4_out}<=2'b00;//关闭外侧2个管子
cnt_open<=cnt_open+1'b1;
if(cnt_open==6'd63) state<=OPEN_ALL;
end
OPEN_ALL://打开外侧2个管子，4个管子全部开放
begin
{pwm1_out,pwm2_out,pwm3_out,pwm4_out}<={pwm1,pwm2,pwm3,pwm4};
if(cs || !fault_and_out || !overcurrent) state<=CLOSE_OUTSIDE;//故障，关闭管子
end
CLOSE_OUTSIDE://关闭外侧2个管子
begin
{pwm2_out,pwm3_out}<={pwm2,pwm3};//内侧2个管子保持
{pwm1_out,pwm4_out}<=2'd0;//关闭外侧2个管子2US
cnt_close<=cnt_close+1'b1;
if(cnt_close==6'd63) state<=CLOSE_ALL;
end
/*SET_INSIDE://1字型备用
begin
{pwm2_out,pwm3_out}<=2'b11;//内侧2个管子强制导通2us，Q1和Q4结电容充电至E/2
{pwm1_out,pwm4_out}<=2'd0;//关闭外侧2个管子
cnt_set<=cnt_set+1'b1;
if(cnt_set==6'd63) state<=OPEN_INSIDE;
end*/
default:state<=CLOSE_ALL;
endcase
end
end

endmodule

仿真时使用的是modelsim-altera，RTL仿真正确，门级仿真看波形以及通过调试发现程序总是停留的OPEN_INSIDE状态，我琢磨好久甚是不透，这里OPEN_INSIDE状态程序不可能有竞争冒险的

Memory00 · 发表于 2022-7-11 17:03

你的问题是个典型的case所包含的项没写完整
cnt_open和cnt_close在case在其他状态不会被reset，直接就死了

oewqe · 发表于 2022-7-11 17:28

再看看别人是怎么说的

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cpld/fpga RTL和门级Modelsim仿真不一致问题

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