|
|
EDA365欢迎您登录！
您需要 登录 才可以下载或查看，没有帐号？注册
x
最近在学习quartus ii 的ddr2的ip核，编写了一个程序，在程序中实例化了DDR2的ip和，想用modelsim仿真看看波形，仅仅是功能仿真（RTL仿真），但是仿真出现了很多一样的错误，如下，请问各位大神遇到过这种情况吗？是怎么解决的？
; p; `, R4 I8 F4 n; G) T2 a. N
* I; s( g: a$ \7 L1 \! z8 l# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_MEM_IF_CS_WIDTH' not found for override.5 F% h) j7 h: V9 j7 V: M! I+ ^
# 5 I0 m- l+ e/ p0 w9 r/ M% w6 C
# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst" C: N% b( @3 o
# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter 'CFG_RANK_tiMER_OUTPUT_REG' not found for override.
( n- D. B- @: }9 l#
6 c- V5 z& A$ w3 A; k: A# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
$ D8 Y+ B+ ^1 J ~# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2328): Module parameter 'CFG_RANK_TIMER_OUTPUT_REG' not found for override.
, t7 | C+ @0 O* B# " S. x* y: w( h, s
# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
$ m# G4 J9 Z4 x n6 ^% j# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2508): Module parameter 'CFG_CTL_ARBITER_TYPE' not found for override.. R. E2 ^8 j5 V( J# ^1 ^
# : {7 z2 \/ x7 g2 D4 v# n( Z- L
# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst
9 W5 w9 U$ F$ l* T: b, Z/ t! k# Loading a0.alt_mem_ddrx_mm_st_converter
. _* T: F% L; _+ O& m4 {# Loading oct0.altera_mem_if_oct_cyclonev E4 t; B* }' q1 a; M4 u/ }
# Loading dll0.altera_mem_if_dll_cyclonev* J4 o+ x) Y9 n0 M* j
# Error loading design2 x8 f% M% Y! b8 j6 A4 e" m
# Error: Error loading design 3 V; G* `( @5 Z6 N) p) N
# Pausing macro execution $ X! M0 R4 V& O1 m2 {
# MACRO ./ddr2_ceshi_run_msim_rtl_verilog.do PAUSED at line 214
b$ Z4 ?2 J: Q% D ^: } |
|
/1 
发表于 2021-11-26 15:48
收藏
淘帖
支持！
反对！