基于FPGA的单稳态脉冲展宽电路的设计问题！

marshal403006

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
计数器（控制展宽电路的宽度）部分：
0 h/ x7 }  u( `9 ~$ Flibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
. e0 f, q0 P( Juse IEEE.STD_LOGIC_UNSIGNED.ALL;
; a: u* f4 J3 }8 B7 k) R. bentity counter is
0 m2 c$ ^4 Y4 E8 Q7 ]( b& g2 u* h  port(reset,en,clk: in std_logic;
+ z3 d; p8 T6 G& j       N1,N2,N3,N4: in std_logic;
+ p3 _/ x  z; t& f$ E8 k       feed_out: out std_logic);
  end counter;
2 G( M) h( x7 T4 t  harchitecture Behavioral of counter is
' r( A3 _$ L4 m; X( V* y$ Esignal temp: integer range 0 to 15:=0;
signal k:integer:=0;
begin
process(N1,N2,N3,N4,k,clk) is
- \+ q% ^) ~( t# e' D: kbegin
1 U& q( ?. ]$ {/ y+ ?   if(N1='1') then temp<=temp+1;
  elsif(N2='1') then temp<=temp+2;
  elsif(N3='1') then temp<=temp+4;
0 B# b' R, ?. I) O  elsif(N4='1') then temp<=temp+8;
4 f4 L3 r* v  s5 B, t) P0 x  else null;
: s0 b+ u' w2 U; y  end if;
: y( H) E' p8 E& ?% L: L' u  if (clk'event and clk='1') then
% B0 e% C! M7 \. E/ ?) f/ A( R0 ?    if (reset='1') then
       k<=0;
     feed_out<='0';
1 t) v% e. e* i! D     elsif (en='1') then   
1 j$ U, ?5 [# R, p  ?( ?4 |, `    if (k=temp-1) then
         feed_out<='1';
         k<=temp-1;
: B% f# K( q# t# W/ ]2 X     else k<=k+1;
3 d: X: k' F% P/ L( Y3 ]    end if;
    end if;
# b8 e- q+ N* l7 o2 q5 Wend if;
# ?- S- T- k* p( ?- L" Kend process;
end Behavioral;
" W; }8 z3 I, R! zD触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
+ l2 a* B9 s* n1 D0 M6 L1 [use IEEE.STD_LOGIC_ARITH.ALL;
& N7 X* Z7 T* L" N; G. y! F' Tuse IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D_trigger is
  M* T3 g' P' q  port(D,clear: in std_logic;
       clk: in std_logic;
' A$ ]( V: A* v% o$ r& }   Q: out std_logic);
  z, R$ e! ]) M, C! ~end D_trigger;
architecture Behavioral of D_trigger is
8 D$ h" m, p. Q* m7 h% ^begin
process(D,clear,clk) is
begin
  if (clear='1') then
    Q<='0';     
  elsif (clk'event and clk='1') then
    Q<=D;
  }9 R. e" L' k8 p4 @9 k  end if;
end process;  
9 [2 T. @" X$ p6 b, M( c( C* {5 Aend Behavioral;
; S9 w6 ~" ^5 Z" f: o. @! F& F外部综合部分：
library IEEE;
* W% }/ o. i% Huse IEEE.STD_LOGIC_1164.ALL;
' Z6 F5 k6 Z2 h- vuse IEEE.STD_LOGIC_ARITH.ALL;
1 ?4 V: u) B2 y& W8 Uuse IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_expand is
  port(pulse_in,D_in: in std_logic;
" J4 l; K& Z5 `" b       clk_in: in std_logic;
& M" p- c( w0 E+ y   n1,n2,n3,n4: in std_logic;
   pulsewidth_out: out std_logic);
end pulse_expand;
architecture Behavioral of pulse_expand is
signal a1,a2,a3: std_logic;
component counter is
5 j4 p$ t4 e+ W3 u. q+ j   port(reset,en,clk: in std_logic;
      N1,N2,N3,N4: in std_logic;
8 d4 I: k6 p2 [4 W7 s7 d        feed_out: out std_logic);
  end component counter;
  component  D_trigger is
     port(D,clear: in std_logic;
          clk: in std_logic;
      Q: out std_logic);
' [- n# m  ~! L4 j0 k/ D  end component D_trigger;
begin
( L5 v4 o% B# Y1 i+ tP1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
a3<= not a2;
/ m) C2 _  ~7 {( n4 R4 XP2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
0 K% B, Q7 W% w. k* o    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
  S: Q) R- N1 K+ S& G' Y; X" Cpulsewidth_out<=a2;
end Behavioral;

6 _/ R' ]  W) U! @8 X! d2 f[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]