基于FPGA的单稳态脉冲展宽电路的设计问题！

marshal403006

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
3 r* T4 y3 `2 B$ T  _8 U( @4 k计数器（控制展宽电路的宽度）部分：
2 Z: s+ T: B6 q& ~4 ]$ b( Wlibrary IEEE;
8 Y) [  S$ x7 X. q- Euse IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
  port(reset,en,clk: in std_logic;
1 k2 S1 e( O. C2 c5 S       N1,N2,N3,N4: in std_logic;
       feed_out: out std_logic);
  end counter;
architecture Behavioral of counter is
signal temp: integer range 0 to 15:=0;
& C  b& M: \& C, t3 \) D! s( Osignal k:integer:=0;
begin
process(N1,N2,N3,N4,k,clk) is
begin
   if(N1='1') then temp<=temp+1;
  elsif(N2='1') then temp<=temp+2;
. t0 U% R2 q3 n* A, S' H  elsif(N3='1') then temp<=temp+4;
& f2 E/ f) |( A. K  elsif(N4='1') then temp<=temp+8;
  else null;
8 ?3 @, H+ a7 Y4 B  end if;
2 J7 L" b- R% G1 L3 `4 p3 u  if (clk'event and clk='1') then
$ k/ j0 c  D% Y. `: I) {. S6 m: j# c    if (reset='1') then
       k<=0;
     feed_out<='0';
     elsif (en='1') then   
    if (k=temp-1) then
/ ?2 [- k+ K. a  H. [: I         feed_out<='1';
1 a/ b: m9 m4 K# Y         k<=temp-1;
     else k<=k+1;
$ B$ W/ s* D3 k' t    end if;
    end if;
end if;
end process;
end Behavioral;
8 g$ m; |$ d$ Z/ `6 nD触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
library IEEE;
$ m& }7 l* Y3 Wuse IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
) F  s& g: D! n& Puse IEEE.STD_LOGIC_UNSIGNED.ALL;
, k1 s# i; M4 N- n8 r* G$ centity D_trigger is
  port(D,clear: in std_logic;
) S' `# ]& R- N: g6 o       clk: in std_logic;
$ e) Z) q+ E! z( j+ V% v   Q: out std_logic);
end D_trigger;
architecture Behavioral of D_trigger is
% g8 a7 g, u% zbegin
' R& r6 o" C' x% \5 _" }& qprocess(D,clear,clk) is
" C% i! L% Q8 ?- W$ L2 Ibegin
  if (clear='1') then
) ]1 g0 r' Z. O# j    Q<='0';     
  elsif (clk'event and clk='1') then
    Q<=D;
* H5 g# `$ |2 [  end if;
7 }0 b4 [7 j" Uend process;  
end Behavioral;
9 a2 W4 t" V$ m6 n0 O+ U# N外部综合部分：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5 J/ j# u- i, s. y5 \entity pulse_expand is
' y" O% a2 c7 H" q; M  N7 X3 Z  port(pulse_in,D_in: in std_logic;
! u8 i. l4 u9 R       clk_in: in std_logic;
4 q7 {( Q' [4 ?% z" J5 k9 @9 Y   n1,n2,n3,n4: in std_logic;
6 {2 V8 n( B$ x( U   pulsewidth_out: out std_logic);
end pulse_expand;
+ J  R- i. N! |# }4 ?6 H' q' Parchitecture Behavioral of pulse_expand is
signal a1,a2,a3: std_logic;
component counter is
4 @- W4 A1 l& @7 B( {+ c1 _1 r  a: ^   port(reset,en,clk: in std_logic;
( z3 u% S8 M& Z  o, p& k2 e      N1,N2,N3,N4: in std_logic;
& S& k. ]& H! U+ W; U/ X4 q0 W        feed_out: out std_logic);
  end component counter;
  component  D_trigger is
1 N4 _" V1 L8 o( E+ E, ~     port(D,clear: in std_logic;
          clk: in std_logic;
      Q: out std_logic);
  end component D_trigger;
begin
P1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
a3<= not a2;
P2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
pulsewidth_out<=a2;
end Behavioral;

[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]