基于FPGA的单稳态脉冲展宽电路的设计问题！

marshal403006

请各位高手看看本人的程序，编译通过了，仿真却没有结果。我想实现的功能是单稳态脉冲展宽（通过外端口控制展宽宽度）。程序如下：
计数器（控制展宽电路的宽度）部分：
$ C8 o0 D* ?( S( }library IEEE;
% Z  u, {& s7 U) ~( Y6 }use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
2 F) r* W7 o. a" M% ~1 W6 G% }entity counter is
  port(reset,en,clk: in std_logic;
0 k, P8 ?5 }* W6 X* v       N1,N2,N3,N4: in std_logic;
       feed_out: out std_logic);
' X+ q: U" d) ]1 \% @8 H  end counter;
) f5 z" ?, t3 j/ }8 D" Tarchitecture Behavioral of counter is
4 C2 _- X$ R. \8 |' {signal temp: integer range 0 to 15:=0;
signal k:integer:=0;
begin
8 D+ x& h; A) M$ D8 i/ Y" I8 Rprocess(N1,N2,N3,N4,k,clk) is
( r: o2 v+ k6 v2 Rbegin
8 n# U$ i/ q/ `1 u0 g( P6 E+ B- G   if(N1='1') then temp<=temp+1;
  elsif(N2='1') then temp<=temp+2;
  elsif(N3='1') then temp<=temp+4;
! w1 i8 @+ W, s  elsif(N4='1') then temp<=temp+8;
6 U1 f" N- x& w3 D- z7 f  else null;
. J8 j* l) A, ~  end if;
  if (clk'event and clk='1') then
    if (reset='1') then
       k<=0;
     feed_out<='0';
( `, Z+ V& C+ h. i     elsif (en='1') then   
    if (k=temp-1) then
7 v* l+ d" O" ]( z9 P9 X' U         feed_out<='1';
         k<=temp-1;
     else k<=k+1;
    end if;
    end if;
end if;
  @6 ^& l1 H( k3 i1 c3 Qend process;
/ e( A% E; z; M% H0 z5 ]end Behavioral;
" V0 m: X$ q# d) l: i% tD触发器（脉冲前沿产生电路，又是展宽脉冲宽度形成电路）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
7 n+ R) G; p) cuse IEEE.STD_LOGIC_UNSIGNED.ALL;
4 T/ `  H# b7 \entity D_trigger is
  port(D,clear: in std_logic;
9 F1 x6 ^# A4 C       clk: in std_logic;
   Q: out std_logic);
: T- t9 S' W2 }6 Q1 r( O, tend D_trigger;
architecture Behavioral of D_trigger is
begin
1 f3 b5 e6 S7 ]( L- [. _; `8 Q0 rprocess(D,clear,clk) is
) m8 E3 N1 X! j4 ~/ Pbegin
  if (clear='1') then
9 O( ~; j$ J. r& L6 n    Q<='0';     
7 e9 D# b  l, _. O  elsif (clk'event and clk='1') then
0 p" I+ i* e) Z/ F8 l; M    Q<=D;
  end if;
end process;  
/ O2 D. k0 E7 \5 L; n5 ?7 Tend Behavioral;
外部综合部分：
/ d5 O4 W: D0 O* s8 X6 klibrary IEEE;
3 R- v2 r9 [6 W: M/ I" z" ?use IEEE.STD_LOGIC_1164.ALL;
& j( g8 [2 |( n8 D% Luse IEEE.STD_LOGIC_ARITH.ALL;
" P$ u% `  V/ M  D, H3 g5 L% |use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pulse_expand is
7 o7 Z  W' G4 X7 U2 P# p  port(pulse_in,D_in: in std_logic;
       clk_in: in std_logic;
   n1,n2,n3,n4: in std_logic;
   pulsewidth_out: out std_logic);
  L: o- E* T$ g. r. nend pulse_expand;
architecture Behavioral of pulse_expand is
signal a1,a2,a3: std_logic;
5 B! `8 b7 c  |( Z% fcomponent counter is
# g2 v& \" Z+ G6 U   port(reset,en,clk: in std_logic;
      N1,N2,N3,N4: in std_logic;
0 Q, q/ G9 \- Q& l- S( o2 C        feed_out: out std_logic);
" p2 r, C: n0 }$ k2 f: A/ r  end component counter;
' z! R9 ^  i& u1 @& Y+ |/ y3 O/ T  component  D_trigger is
- p1 g/ g  M: O# i- i     port(D,clear: in std_logic;
          clk: in std_logic;
      Q: out std_logic);
  end component D_trigger;
begin
P1: D_trigger port map (D=>D_in,clear=>a1,clk=>pulse_in,Q=>a2);
3 N0 G7 u) }5 @( @2 l: O9 R& w) Qa3<= not a2;
2 }8 W0 z/ b# R  s# \5 FP2: counter port map ( reset=>a3,en=>a2,clk=>clk_in,feed_out=>a1,
* v. p0 I# }# F- a! |- `    N1=>n1,N2=>n2,N3=>n3,N4=>n4);
pulsewidth_out<=a2;
" p1 p4 B8 _, k% M* V2 |end Behavioral;

* D: c$ S$ U4 H) _' o( a[ 本帖最后由 marshal403006 于 2008-6-2 09:38 编辑 ]