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EDA365电子论坛网»电子社区 › EDA工具&PCB设计 › Mentor Xpedition论坛 › ForwardAnnotation.txt 哪里有错误
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ForwardAnnotation.txt 哪里有错误

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mentor.

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发表于 2011-5-5 22:21 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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本帖最后由 mentor. 于 2011-5-5 23:15 编辑
) |1 _, _' `0 ~/ j- h5 i5 q! J! v; q' S2 N8 v: \
         Forward Annotation
( Z' Q0 j0 T( h* C6 l' y                               ------------------
+ p) q  m: [8 e7 q0 j4 R0 {                         10:19 PM Thursday, May 05, 2011
* Z7 X5 N4 v1 x5 ]. i                Job Name: C:\WDIR\MyPrj\NIOS\NIOSii\PCB\NIOS.pcb5 X1 o* X. p) Y% Y% {# m

* s7 W0 x1 v/ E0 [Version:  01.01.001 g7 c6 v  r+ f0 r/ a
     The PDBs listed in the project file will be searched to satisfy the parts5 B& U4 |( l; \( }% z
      requirements of the iCDB only for parts not already found in the  v, K7 z3 w$ D* [
      Target PDB.6 T6 ^0 K$ V. a, p/ n2 k
     The schematic source is a Common Data Base.
- D. E1 n# d$ Y5 h$ q3 z/ h8 [3 ]6 v     The AllowAlphaRefDes status indicates that reference
. @) h9 z  j; U  B5 z      designators containing all alpha characters should be deleted. j2 J- c4 |3 i# X% i
      and the relevant symbols repackaged.
7 u+ M8 s9 F- c) F) r6 \+ L" f0 `6 Y
     Common Data Base has been read
4 k7 A8 H. T( r* I. T     Target PDB Name: Work\Layout_Temp\PartsDB.pdb/ O4 H8 j2 E1 w
     Number of Part Numbers: 200 R# J  S& E6 I( G8 w  K4 r
          Part Numb: AMS1117 -> Vend Part: AMS1117 + W: b/ n% T$ y- \" d
          Part Numb: Cap220UF -> Vend Part: Cap220UF 1 F8 ]- [" `; N
          Part Numb: Cap0805 -> Vend Part: Cap0805
4 c' J4 Y& g: J) T& }          Part Numb: Cap1210 -> Vend Part: Cap1210 $ V8 k# g/ t7 [: o9 L- ?: M# H' |
          Part Numb: Cry_50M -> Vend Part: Cry_50M * F7 a" G: [) A# m" m
          Part Numb: DC_POWER -> Vend Part: DC_POWER
2 j/ P- R& K. Z0 y8 C          Part Numb: EPCS4SI8 -> Vend Part: EPCS4SI8 4 f% F) v; v$ }- A5 a
          Part Numb: EP2C8Q208 -> Vend Part: EP2C8Q208
: O1 E+ x. z! n; X          Part Numb: FB -> Vend Part: FB
3 ~7 A& z/ C7 m          Part Numb: Header10 -> Vend Part: Header10 6 v! Z3 I% K7 Y) V) t, q# v/ R
          Part Numb: Header25x2 -> Vend Part: Header25x2
, M& _9 l) }: Z% l/ t          Part Numb: IS61LV25616AL -> Vend Part: IS61LV25616AL : d" k: w) F, o& Z  S( u3 P
          Part Numb: JS28F320J3D -> Vend Part: JS28F320J3D / t7 c1 q9 [5 G
          Part Numb: K4S281632K -> Vend Part: K4S281632K 9 x8 l: C5 R7 u- L" @; W- A0 K1 h; R
          Part Numb: LED -> Vend Part: LED + ^! ]0 I# A7 @# E' c" S: o1 C
          Part Numb: Res0805 -> Vend Part: Res0805 2 t# |. }6 y  f
          Part Numb: SMB -> Vend Part: SMB
. V( g& y# b- F          Part Numb: SW -> Vend Part: SW % m/ X! ^' y6 a8 q
          Part Numb: SW_90 -> Vend Part: SW_90 0 p2 Q+ |0 w# h
          Part Numb: SW4 -> Vend Part: SW4 ) @+ `! G" n6 D) L5 U
     Number of Part Names: 09 s1 Q& j7 i3 s$ D  f
     Number of Part Labels: 04 t% x  e' \7 @  F. C
- R8 h+ I6 I/ ]; D% `9 @

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mentor.

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2#
 楼主| 发表于 2011-5-5 22:22 | 只看该作者
Checking for value differences between symbol properties and PartsDB properties
* t* c) g: s9 v) `0 P6 b% p! E) m1 r" `# o
     Checking the validity of the packaging of prepackaged schematic4 ^; I) v+ w. K( V
      symbols.  Only the first error in symbols having the same
* \# ]! _9 {: [: ?# a- o& f      Reference Designator will be reported.
3 R/ D3 \" F3 r3 i# O% H
) r* U, \% w+ l) W! E     The packaging of all prepackaged schematic symbols is consistent# L7 d" Q, _; s  ?
      with the Parts DataBase data for the cross mapping of
  H# v9 K/ p3 l6 s' ]      symbol pin names to Part Number pin numbers.
+ ]) d1 H0 R* o! V6 p5 O9 K      Symbols that were not prepackaged will now be packaged correctly.8 P) ?9 b7 i- g0 a5 p: e$ L
      
$ ]& X8 e- V7 d; J$ b6 X6 D/ o     No errors in Existing Schematic Packaging.
- B0 e& _4 Q/ B1 y* G. b/ `
# `8 H" c- C( R6 L( C5 O' Q     The Common DataBase has been read and will be packaged.: j6 m0 k, L8 c4 B
     Clustering 109 Symbols:* i+ a- X' I( Z) e
             109  ********4 e# [# |' J# v, \7 w% L  a: M
             100  **************************************************
: w: _# S7 [$ U              50  **************************************************/ N; Q- Q$ L  ]# J9 z
     Clustering is Complete1 q: f% @- |  y: I) X! h: k9 B

  C1 Q4 ^; N! @  V& h6 O     Packager Assignments successfully completed
1 I# {' @1 `" Y

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3#
 楼主| 发表于 2011-5-5 22:23 | 只看该作者
187 nets were found containing 676 pins: N2 ]  n8 |9 [5 `
     101 components were found9 F' l/ ^3 S' \. m
: O2 U2 a; N& P  p
     WARNING:  Cell  could not be found in the CellDB for
& b, P6 t5 L' t/ C4 x      Part Number K4S281632K.
9 G$ E) S' t$ G4 R0 B7 K- t% @- S2 V/ N7 I
     WARNING:  Cell  could not be found in the CellDB for, a4 J  }0 j& o: M! ~( K
      Part Number IS61LV25616AL.& Y$ J4 i, t: q5 D& B

$ K/ D# r* z% b+ M! _" K" |( d; M     2 Pin application warnings found as noted above.
6 E& I6 l4 j% F/ A7 C! Z' L5 D8 u8 T5 K! A# e
     Creating a formatted Schematic Netlist (LogFiles\SchematicNetlist.txt)...' w+ j* J9 ~, \0 O" z* F
     A formatted Schematic Netlist has been created.  z+ R7 Z4 z6 b3 f* K; n# ?6 o

4 ~- g2 k6 y  G3 t     The Logic DataBase has been compiled from the Schematic Design.
' `, u2 L8 k# H# Y0 x      Use Netload to bring the Component Design into sync.  B2 [* w8 ?, m: @' ]8 y$ T1 s0 m# w

% J6 C* t* M/ j: {0 R     This Logic Data was Compiled with 2 warnings.0 M# p, }4 a, e9 B2 S# Y, u
      Erroneous results may occur if not fixed.. d* M; C$ J& j! U. r

1 x0 o% R& ~  z2 k: A                                     NetLoad$ v- O+ Z3 O! k1 {3 R  a+ H  g
                                     -------7 [/ V2 K" ~8 Z) x( O- d  [' L

: w: U9 ~/ A- f& G                         10:19 PM Thursday, May 05, 20112 d8 `% n8 N3 X8 j' l/ i3 M2 A5 n
                Job Name: C:\WDIR\MyPrj\NIOS\NIOSii\PCB\NIOS.pcb+ p& v: t! g9 i

: S& i2 B) P/ m) x* E" p  p- e3 I, T- W# t& f) w# V8 q
Version:  02.11.12
, o8 F7 |% d0 A' c" o3 ^
  q9 G% b8 ?% h. T" C        Netloading the Layout.  Unused components will be changed to spares.
5 ^9 _" D6 w% x7 n# ^5 ?2 Z
. ?+ r; Z; w/ W5 x1 p7 H$ l! |0 [        Unconnected pins will be set to net "(Net0)".
0 w1 w- Y' k% P+ G7 ]( u# @% W! ^2 d( @7 p! S
        Schematic reference designator changes will be forward annotated.
% M& t( u' o( t1 _: [6 g7 d2 k. ?' a$ e% b, P% o' E8 j5 L

0 i) c" ~' p4 z8 }     "C17" is being converted from a spare to a "Cap0805" part.
6 f9 \2 G" n/ @) D, n: H2 H2 S5 m% l" `4 f' O1 }6 y
     Netload completed successfully with 0 warning(s).
4 ]  N+ N* j$ d9 ~     
# w9 K+ x4 d' M     Back Annotating...7 Y9 G# a$ o7 S0 T- ~  {9 K
& i; c/ z, p. P/ p3 ?
  Updating Logic Database...+ z: R$ g! i0 {( x( r: U1 e  q, G

7 s2 Y1 m/ h$ j4 ?% M; b6 [0 q     Version:  99.00.05/ r8 S" K) y$ g$ A( O' {
* v+ d3 K4 z: v
     No changes made to Existing Schematic Packaging.: e7 \" S6 B: ?, H& H% S

& `1 |6 N& p5 S% `3 g+ c# `
: C1 w4 z$ m( ?* ^+ y6 ]+ {     There is no symbol data to be back annotated to the schematic source.

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4#
 楼主| 发表于 2011-5-5 22:24 | 只看该作者
  The Logic DataBase has been updated and the Common DataBase has
/ d2 m( _3 s3 P7 [  E. D0 ?      automatically been brought into sync with the Logic DataBase.
, q  |$ O+ R/ S      Please proceed with your design.$ _1 m# o/ X8 L( ^3 m
$ h$ n( r/ M  i1 \! P6 e: G  \2 `
     Finished updating the Logic Database.
* V! m: P2 p! \1 A7 @  ]. k& [6 ~9 L/ R) |* I/ T4 U
     Creating a formatted Schematic Netlist (LogFiles\AfterBakAnnoNetlist.txt)...9 p7 o3 @3 T% Y* T6 F  j/ M9 Q' a2 R7 I
     A formatted Schematic Netlist has been created.+ }% e4 |( ?; x8 h
1 a. J2 X  Q# L0 `) h7 _
     Creating a new netlist text file (LogFiles\KeyinNetList.txt)
7 L: I+ ]+ n9 [; H: W      from the Logic Database (Work\Layout_Temp\LogicDB.lgc)...
& \3 z" G6 n4 j4 l' J; Y3 @) \" n  A new netlist text file has been generated.
" X6 o& ~; H9 K
4 H- X" G9 F7 C* X; U+ b. A  Z3 M! E
$ y. q- E& l0 W
                 Beginning Netload on the Layout Design.3 h$ I& U2 {! m: s9 F' P
           ---------------------------------------------------- k  f% k; ~! {5 u# [- d$ H

( b. [5 k, A/ H0 P) }% ~( QForward-Annotation on the Layout Design has been successfully completed.
9 y1 i2 u* A  ]6 F% ?4 u& N6 c# l! x8 D" e5 f  x+ u8 k
There were 0 reassignments of nets.
1 k! M' {7 @' f6 d; I4 W) PThere were 0 traces broken back.' }' V: A( @7 n/ x6 o' z5 \- s
There were 0 nets removed from the Layout Design.

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mentor.

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5#
 楼主| 发表于 2011-5-5 22:28 | 只看该作者
这是一个forward 的log, 是什么原因不能Foreard 呢？

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6#
发表于 2011-5-6 17:42 | 只看该作者
  WARNING:  Cell  could not be found in the CellDB for
0 c; [) W( w. x- V+ o. C      Part Number K4S281632K.
2 K, h* I' k" f1 x) V* k- G) G' \6 ~; Q) i7 @9 ^: i0 S, c* c1 l: T5 U0 r9 \( t8 ~
     WARNING:  Cell  could not be found in the CellDB for6 ^+ {. Z. ~+ T
  Z: [( i, q+ q: W# D5 M      Part Number IS61LV25616AL.6 b* A3 T" E2 _  q! |. ~
这2个元件是不是在原理图里面更改了part number。导致LIB中不能调入？

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