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最近在做有关FPGA的仿真,在ISE中约束管脚和电平后,生成IBIS模型,可是仿真时出问题,拓扑结构能够提取出来,但是仿真时提示"cycle.msm does not exist"tlsim里面内容如下:9 ^8 Z& C% F! x! b- ?& V/ U5 t2 r. s
**** Tlsim command line ****
5 }8 I5 o+ D3 R2 a$ u tlsim -e 2.000000e+001 -r 0.200000 -o waveforms.sim -dl delay.dl -dst distortion.dst -log tlsim.log -ocycle cycle.msm main.spc' w h; p9 m P- A: a
4 `( S( I& ]% D" ^*********************************************************
9 m6 d: y! o$ P7 @, I Failed To Compile SubCircuit xUHF==RECEIVER_icn_ckt 1 UHF==RECEIVER_icn_ckt8 k9 Y) Q8 P6 i) |1 [
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*********************************************************
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*********************************************************2 h. f7 ~7 j/ N5 [- l
ABORT:The Circuit is Empty % l. l# `6 g& t' s2 ~* W. P. v5 s
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! _, s+ j* P+ A, {+ f! E( f5 F在audit所仿真的网络时,有错误:5 M. S4 K, z1 y+ B
ERROR >> Pin(s) with conflict between PINUSE property
4 V* {9 X# T- h, [, W) | and signal_model parameter in IbisDevice pin map :
% R5 C- |% Y9 A, h5 T$ b Pin Component Pin Use Signal Model Design
7 Q2 o ^' L: E$ D0 f* A$ g3 q* a --- --------- ------- ------------ ------
1 x- t$ w& F, V! R8 s9 a4 x6 P+ F: Y B4 U11 NC SPARTAN6_PINASSIGN_LVDS_33_TB_25 UHF==RECEIVER+ C! K5 O) e- a" _# @( l, ?# ]! Z6 Z
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9 b# p6 M2 @8 q6 g# H请各位大侠帮忙!!!多谢!!!; |# O" @8 c" |7 n6 o! F7 y
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