#技术风云榜#play with OpenRISC based atlys board（3）

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#技术风云榜#play with OpenRISC based atlys board（3）

! G: D' Z7 l8 `#技术风云榜#play with OpenRISC based atlys board（1）：https://www.eda365.com/forum.php?mod=viewthread&tid=469239&page=1&extra=#pid2131573
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3 i2 Y# K6 w0 }  m/ t#技术风云榜#play with OpenRISC based atlys board（2）：https://www.eda365.com/forum.php?mod=viewthread&tid=469267&page=1&extra=#pid2131619
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3.Using ORPSoC

Introduction


5 d9 x" d; Q# x' ^# k3 W: C- u  [ORPSoC  is intended to be a reference implementation of processors in the OpenRISC family. It provides a smallest-possible reference system, primarily for testing of the processors. It also provides systems intended to be synthesized and programmed on physical hardware. The reference system is the least complex implementation and consists of just enough to test the processor’s functionality. The board-targeted builds typically include many additional peripherals. For more information read the  ORPSoC User Guide  found in the doc directory of the ORPSoC installation.
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Project organization
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The ORPSoC project is intended to serve dual purposes. One is to act as a development platform for OpenRISC processors, and as a development platform of OpenRISC-based SoCs targeted at specific hardware. Organising a single project to satisfy these requirements can lead to some overlap and redundancy. The reference implementation based in the root (base directory) of the project contains enough components to create a simple OpenRISC-based SoC. Each board build is intended to implement as fully-featured a system as possible, depending on the targeted hardware. The project is organised in such a way that each board build can use both the reference implementation’s RTL modules and software, as well as its own set of RTL and software. The reference implementation is limited to what is available in the RTL and software directories in the root of the project, and is not technology dependent.
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+ E6 m& \5 J5 o4 E: X. PThe Atlys board

We will start by finding the Atlys board setup.

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0 J: K9 J- ~; Z& F9 h; h. lBefore we start

Before we start the design phase we have to make sure the Xilinx  Design Suite is installed and that the environment variable XILINX is set.

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Design
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/ ?% K# K$ t9 fThe design is made up of a number of Verilog HDL files. They reside in two different directory. One directory that holds all the code that is common to all board designs found here:
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" j+ A+ q, Y, J9 A& g& \And one board specific design directory as shown in the screenplot of the atlys board directory structure. The syntesis script will pick up all the Verilog design files to build the complete system.
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Synthesis

Synthesis of the board port for the Xilinx technology with the XST synthesis tool can be run in the board’s <syn/xst/run> path with the following command: <make all>
" \0 ?- L( I# ~6 g4 l' M2 z- @7 RThis will create an NGC file in <syn/xst/run> named <orpsoc.ngc>. Hopefully it’s all automated enough so that, as long as the design is simulating as desired, the correct set of RTL will be picked up and synthesized without any need for customising scripts for the tool.



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& e. y; o  p& a8 sUser constraints file
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A Xilinx User Constraints File (UCF) is in the board’s <backend/par/bin> path. It is named <atlys.ucf>. It should be edited if any extra I/O or constraints are required.


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Mappping and place & route


Mapping and place & route of the design can be run from the board’s <backend/par/run> path with the following command: <make orpsoc.ncd>. The makefile used can be found in the <......./boards/xilinx/atlys/backend/par/bin> directory. Here is an excerpt from the makefile showing the backend design flow:
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6 z5 ?$ y) t/ n/ b$ ^Place & route results


' u, u; ~5 Z) U. G+ ~The results from the place & route tool can be found in the logfile <orpsoc.par>:
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Options

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To get a list of options that can be set when running the backend flow, run the following command:

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* ]1 Y- v! @3 u2 k2 Jmake print-config
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8 w, n2 z5 R) y( ~: Z. rGenerate timing report


" d6 l' J4 f- r. ~! j7 O- rThe trace tool can be used to generate a timing report of the post-place and route design:

' m2 q( l  p6 B! Hmake timingreport

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. v* q1 F6 V& Q" t& Y0 |5 {% fHere is the result:
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We have 1338 timing errors. Before we continue we have to investigate these errors. The timing report result file is called <orpsoc.twr>. Analyzing the this we find the following timing errors.


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Without knowing to much about the design it is hard to figure out what is wrong. Let's setup a simulation environment and analyze what's going on (see next chapter).

' W" g* m5 ?0 j" ^Generating the bitstream file
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The bitstream file is used to configure the FPGA device. The configuration file generation is run from the .../atlys/backend/par/run directory using the command:  make orpsoc.bit
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' ~; w5 @5 ?4 g3 `Downloading the bitstream

We are going to use the Xilinx configuration tool called iMPACT to configure the SPARTAN-6 FPGA on the Atlys board. The first thing we have to do is connecting our board to the computer we use for our development work using a USB cable.
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Then start iMPACT.


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4 D- s. v8 _7 I1 A7 _We will create a new iMPACT project.


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& v5 ]& S+ T9 | We are going to use JTAG to configure the device.

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) I( ?+ G  M  U5 wThe iMPACT tool will connect to the boundary scan chain on the board and identify the FPGA.


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To add a configuration file we right-click the FPGA icon and select <Assign New Configuration File> and find the configuration file <orpsoc.bit>.
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  b: ~2 ~) {9 V+ f( C3 oWhen double-clicking the Program operation entry the configuration will start. After a few seconds the configuration has finished.
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regngfpcb

play with OpenRISC based atlys board