|
EDA365欢迎您登录!
您需要 登录 才可以下载或查看,没有帐号?注册
x
刚接触SQ仿真,遇到如下问题,请高手们不吝赐教:
8 ?, N) R4 q3 l0 [2 V1.将IBIS模型转化为dml格式后,在Signal Model Assignment界面下,赋给芯片相应的模型后,发现芯片有部分管脚使用赋给的模型,而部分管脚却使用系统黙认的模型,这是为什么?编辑模型时,提示错误如下:0 s" z D) W0 R
model Hi3520V100_PBGA768 defines pin Y04 which doesn't exist in component SN2116_V83_FINAL U9
: W, X# h% ^- J' f% z0 a" @model Hi3520V100_PBGA768 defines pin Y03 which doesn't exist in component SN2116_V83_FINAL U9, ]+ B, f6 [9 U; ~) p. `# { t4 {' A
model Hi3520V100_PBGA768 defines pin Y02 which doesn't exist in component SN2116_V83_FINAL U9
# K7 f; V1 i5 ^. E9 F* f3 n! amodel Hi3520V100_PBGA768 defines pin Y01 which doesn't exist in component SN2116_V83_FINAL U9. I8 j6 f2 `" D+ I$ S* @
model Hi3520V100_PBGA768 defines pin W04 which doesn't exist in component SN2116_V83_FINAL U9
. d! l Q+ v# G! Xmodel Hi3520V100_PBGA768 defines pin W03 which doesn't exist in component SN2116_V83_FINAL U9
0 W9 m9 G, o) p4 p H# zmodel Hi3520V100_PBGA768 defines pin W02 which doesn't exist in component SN2116_V83_FINAL U9+ h! J6 O4 @: p6 E+ w! r6 ]
(注 该芯片是PGA封装,且厂家提供的PIN管脚是字母加数字的)
4 m& P6 N5 M5 u4 X2.提取网络时,在点击Reports查看报告和Waveforms查看波形时,弹出如下警告:+ {& j* I e( Z- U
WARNINGS:& r$ a; {% u7 s6 K3 M
No 'V Measurement' is defined in the delay measurement fixture of model ATP8624_SP018W_PCIX. The buffer delay is assumed 0.* r" J# `' k* d2 m5 Y7 n
这是什么原因造成的?会产生什么影响?' J. _) b) |; r- a3 r1 B) g
再次谢谢大家。 |
|