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刚接触SQ仿真,遇到如下问题,请高手们不吝赐教: l3 G5 Y, G$ r
1.将IBIS模型转化为dml格式后,在Signal Model Assignment界面下,赋给芯片相应的模型后,发现芯片有部分管脚使用赋给的模型,而部分管脚却使用系统黙认的模型,这是为什么?编辑模型时,提示错误如下:
8 g" e8 k9 k$ C+ a! v; @7 vmodel Hi3520V100_PBGA768 defines pin Y04 which doesn't exist in component SN2116_V83_FINAL U9
" j: l! y2 a1 ?4 Pmodel Hi3520V100_PBGA768 defines pin Y03 which doesn't exist in component SN2116_V83_FINAL U9
9 P4 ?( Y- D) R' k4 J8 a# kmodel Hi3520V100_PBGA768 defines pin Y02 which doesn't exist in component SN2116_V83_FINAL U9' U6 W$ p( B, O- z% p. \7 q2 o
model Hi3520V100_PBGA768 defines pin Y01 which doesn't exist in component SN2116_V83_FINAL U9! I2 l4 h1 L* O( ]
model Hi3520V100_PBGA768 defines pin W04 which doesn't exist in component SN2116_V83_FINAL U92 ^( d: }. [2 `. H" D6 k4 J
model Hi3520V100_PBGA768 defines pin W03 which doesn't exist in component SN2116_V83_FINAL U9, ^5 R5 j* B; [
model Hi3520V100_PBGA768 defines pin W02 which doesn't exist in component SN2116_V83_FINAL U9' h! J2 s5 Y: A- Y7 p5 |
(注 该芯片是PGA封装,且厂家提供的PIN管脚是字母加数字的)
& |+ v# ?+ z2 |2.提取网络时,在点击Reports查看报告和Waveforms查看波形时,弹出如下警告:. v6 [8 r5 n. e i" a! Z w( E) t/ ]4 \
WARNINGS:
% ~. l! L# W, Y. cNo 'V Measurement' is defined in the delay measurement fixture of model ATP8624_SP018W_PCIX. The buffer delay is assumed 0.
- f$ C; R% }2 z9 E% b( Q% O这是什么原因造成的?会产生什么影响?8 ~7 F) c3 J! J) o- x+ V
再次谢谢大家。 |
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