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刚接触SQ仿真,遇到如下问题,请高手们不吝赐教:
. K! c5 N: l) j1.将IBIS模型转化为dml格式后,在Signal Model Assignment界面下,赋给芯片相应的模型后,发现芯片有部分管脚使用赋给的模型,而部分管脚却使用系统黙认的模型,这是为什么?编辑模型时,提示错误如下:
& J" i: |- x: i7 v }% Smodel Hi3520V100_PBGA768 defines pin Y04 which doesn't exist in component SN2116_V83_FINAL U9. X7 i% ^, ~: [
model Hi3520V100_PBGA768 defines pin Y03 which doesn't exist in component SN2116_V83_FINAL U9
2 r7 f7 b4 F, S# W2 V! Kmodel Hi3520V100_PBGA768 defines pin Y02 which doesn't exist in component SN2116_V83_FINAL U9/ m3 C- S) F, P$ L! ]2 {+ m
model Hi3520V100_PBGA768 defines pin Y01 which doesn't exist in component SN2116_V83_FINAL U9
9 l9 s6 B+ e& j" o7 ?8 ~model Hi3520V100_PBGA768 defines pin W04 which doesn't exist in component SN2116_V83_FINAL U95 @2 c$ X: ^+ w0 h# ?
model Hi3520V100_PBGA768 defines pin W03 which doesn't exist in component SN2116_V83_FINAL U9- ?! l/ z' E/ [6 r+ B! n
model Hi3520V100_PBGA768 defines pin W02 which doesn't exist in component SN2116_V83_FINAL U9& w0 {% q. f: u2 o4 n5 {
(注 该芯片是PGA封装,且厂家提供的PIN管脚是字母加数字的)
; ?1 z6 J& Y$ @) [9 D+ W. b2 h2.提取网络时,在点击Reports查看报告和Waveforms查看波形时,弹出如下警告:
4 L6 o$ z% g- xWARNINGS:
! q% M. Q x5 A1 F1 v# j: TNo 'V Measurement' is defined in the delay measurement fixture of model ATP8624_SP018W_PCIX. The buffer delay is assumed 0.* O: `/ `, Y4 p) u
这是什么原因造成的?会产生什么影响?$ W+ N, }4 E0 _9 z: i+ q
再次谢谢大家。 |
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