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七人表决器的程序如下
4 O/ r3 \# ^7 o# xmodule voter7(
( L% H# ^4 z% c9 J4 t# U2 D8 j output reg pass,
! U) z( Z- Z ^ input[6:0] vote6 u$ L$ u8 g& M; Y& j* x3 k& u
);5 k0 d" a* T! R' E
integer i; . @' X2 u0 q3 K! K
reg[2:0] sum;
8 n, B' L: w+ K) A8 H+ D7 l3 h initial & l5 B/ P9 S: f% r+ d
begin
7 w! K. K4 X8 `5 `& W. w& c+ U/ n7 | sum=3'b000;+ _1 L" @/ [, P6 u4 X2 p# ^9 h4 q
end
7 P' b' s, O5 P9 c7 W
5 x* M1 H9 T. i# s0 z always @(vote)
8 F( _6 f+ A; N o" e% c9 X begin / i k0 O7 |, F- x
; d/ ^. i: E/ V- `" @ for(i=0;i<=6;i=i+1) //for语句8 g2 h! r, i y% r6 ?0 G# d
begin
( N/ t. p) z" C' x: [, h6 i! N if(vote[i]) sum=sum+1;
3 c& u: J" L6 l, H) X7 |9 V end9 ?+ e! g/ L7 L' d9 q+ M; z! [
if(sum>3) pass=1'b1; //若超过4人赞成,则pass=1
+ y- z f$ K9 ?7 v else pass=1'b0;
- M- r, a! y& V2 b% k7 u8 U, T end
: }0 m% V7 s. }) W$ P8 @endmodule 9 v" {5 C) x# W0 ]
5 h. c% ?6 M- ~' O2 j6 E8 f
- X0 C" P* [. B
& w! V+ W/ P) o5 C0 G9 M. `( `有提示是这样的, K: y/ m. L0 S; y- j
Warning (10235): Verilog HDL Always Construct warning at voter7.v(18): variable "sum" is read inside the Always Construct but isn't in the Always Construct's Event Control; _ s! Y; B T" ?
" l, C3 A' _9 ^Warning (10240): Verilog HDL Always Construct warning at voter7.v(13): inferring latch(es) for variable "sum", which holds its previous value in one or more paths through the always construct
3 [% z' @$ a' X! I/ l6 _. t+ E# G! T2 w/ c9 [6 i. q
仿真的时候pass信号为未知状态
1 q- i8 ^8 Y1 z怎么办呢? |
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