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七人表决器的程序如下
) n& u; b2 G6 Fmodule voter7(
' L7 _& d+ Q0 M' d/ [$ n output reg pass,
/ X% g* i) w! S& g6 [" v input[6:0] vote% V+ K( D+ d8 |$ I& E( B+ ]! U7 V2 c
);
. n# ?& y, k9 h2 ~( R- }3 Rinteger i; " t8 l. m# {! |6 d' m1 o2 X% c
reg[2:0] sum;
) d! t, r% o% j- X7 M initial + x$ V( l8 Q7 u0 }8 C% c! }
begin
% G9 i4 d7 n( m sum=3'b000;, t% d& n( e, L7 }; e4 L1 R
end
, Y# X0 ?+ U7 {) M! ^# f 6 \% ]% g8 ~1 I E
always @(vote)
2 y" i0 Z% H& k' n* D begin
: U! B r& T- d * M! v( C3 V8 N+ M
for(i=0;i<=6;i=i+1) //for语句) v; |( Y( x9 m7 F6 z
begin . r5 ~8 n! Y7 h, Y1 ?, X
if(vote[i]) sum=sum+1; # _5 A. b7 ^, v1 G6 b' n* r
end
0 ?, P9 P/ M' a& W; _$ G& M6 H4 @ if(sum>3) pass=1'b1; //若超过4人赞成,则pass=1
) U; [9 e. W8 ]& r else pass=1'b0;
/ ~% r% U# J$ ?4 t# N0 e- R5 b0 P end
! m9 X# }( t4 {/ Yendmodule ( s: r) l* E% i2 Q; f
$ \1 t8 x8 i6 |) [0 b- n+ `% g2 d6 H% v7 @2 X& [
$ {2 N# g' n$ @2 K! ]
有提示是这样的
9 z$ I$ R3 l. ~: O* G$ c2 VWarning (10235): Verilog HDL Always Construct warning at voter7.v(18): variable "sum" is read inside the Always Construct but isn't in the Always Construct's Event Control
4 Q' N2 K3 Z% v6 I7 p3 B: s
# t8 L; R; a3 S- I; c1 M# aWarning (10240): Verilog HDL Always Construct warning at voter7.v(13): inferring latch(es) for variable "sum", which holds its previous value in one or more paths through the always construct
* d% E9 s% ?% ]7 l l, B# S4 p$ o3 F; E2 M! I9 p% O( g( X3 P- Z
仿真的时候pass信号为未知状态 # b: B- k- S7 v3 J
怎么办呢? |
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