求救—谁能帮忙改一改

zhong0985

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hour is
port(clk_h,clk_t,tp_h,res_h:in std_logic;
  l0 h7 _/ W: P# j, X6 e0 x8 o  hset:in std_logic;
  sig_h:in std_logic_vector(2 downto 0);
  din_h1ut std_logic_vector(3 downto 0);
+ ?  G2 J: w7 x  k$ n/ ]  din_h0ut std_logic_vector(3 downto 0);
  pmut std_logic;
  cp_h:out std_logic);
" z+ y& c0 b: j) X  
end hour;
9 G7 _' z# B4 }% qarchitecture behav of hour is
signal clk:std_logic;
begin
    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
     variable co1:std_logic;
     variable co2: std_logic_vector(7 downto 0) ;
  m  P( v$ o; S; M5 g- E9 R   begin
    if sig_h="001"and tp_h='1' then clk<=clk_t;
   else clk<=clk_h;
   end if;
    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
. i6 }8 S2 N# C, d  T, H5 Q       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
            end if;
# i/ N) b! j8 s& Q* |) b; i            if  cq2="0010" and cq1="0100" then
# T! u' k) ^7 ]+ l/ ~: }6 v% B; M    cq1:="0000";cq2:="0000";
/ P7 X1 o3 v4 t    co1:='1';
   else co1:='0';
5 H1 Z: v0 b$ S      end if;
      if cq3="1010" then
      cq4:=cq4+1;
      cq3:="0000";
. F% O7 [# x1 Z, n    end if;
   if cq4="0001" and cq3="0010" then
         cq3:="0000";cq4:="0000";co2:=co2+1;
      end if;
  p2 G3 B# \. M3 n    end if;
+ o  u- A+ O' P; H( N  if hset='1' then   
" P1 N5 T( W2 M1 h          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
. [& }6 A/ w/ c- c1 e, I         else
8 {$ P! r  ?2 b. T           if co2(0)='1' then
1 {. k- H. i& o3 V1 u, F  v0 y" b% C             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
             end if;
             pm<='1';
" G, w' K5 t+ m/ @% [            else pm<='0';
) h" f/ s5 c, x4 X) E( h* T            end if;
* Y8 z9 k  C# h! B8 D! z            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
              else cp_h<='0';
, s2 m5 S$ w9 @             end if;
           din_h1<=cq4;din_h0<=cq3;  
0 Q1 @% v/ F. K7 d. ?0 \; \+ K- J        end if;  --12/24转换
  
1 m5 m( p' |: S     end process;
* f+ v9 H3 H6 g/ m$ I2 dend behav;

zhong0985

报错：
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
        Info: Processing started: Sat Oct 31 17:04:02 2009
2 B/ k/ t- g# ], DInfo: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
4 T, L# S! l1 D6 w/ [1 b2 xInfo: Found 2 design units, including 1 entities, in source file hour.vhd
        Info: Found design unit 1: hour-behav
8 Z5 f9 c( u' _# u5 F2 F        Info: Found entity 1: hour
Info: Elaborating entity "hour" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
3 d. _: L5 R0 n6 C# k$ lInfo (10041): Inferred latch for "pm" at hour.vhd(20)
0 [1 L* t3 N6 |1 ?6 lError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
; g* P- s9 {; @2 u- X8 rError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
* j. t; ?+ K  c/ cError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
' w; G1 \" X2 b3 \; w        Error: Peak virtual memory: 184 megabytes
3 T0 i$ L# m7 F( z, Y5 A! a        Error: Processing ended: Sat Oct 31 17:04:04 2009
        Error: Elapsed time: 00:00:02
7 O9 d8 R! a* z: N. x% O& ?        Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings