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求救—谁能帮忙改一改

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发表于 2009-10-31 17:10 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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library ieee;, M4 C6 d0 q9 P# u- @- b- x1 _. n9 [* m
use ieee.std_logic_1164.all;
0 J, G. N! V0 [9 y7 B( Tuse ieee.std_logic_arith.all;' ~$ X( k* ?& l2 u
use ieee.std_logic_unsigned.all;
& c& U3 O% t: }8 U* Rentity hour is. R! ?) }1 O9 J
port(clk_h,clk_t,tp_h,res_h:in std_logic;
7 |4 U4 C- _1 O7 ^% J' x4 y  hset:in std_logic;! w' W5 |1 N+ c9 Z. z, }
  sig_h:in std_logic_vector(2 downto 0);
8 }( A: |7 v* l6 Y; |7 @6 E0 t# r' y  din_h1ut std_logic_vector(3 downto 0);
; D; [$ I( [2 t" q3 @+ [, J! v  din_h0ut std_logic_vector(3 downto 0);
1 }3 s! D. J$ G, ^: e  pmut std_logic;$ a1 I6 I6 t# P& e2 r1 A
  cp_h:out std_logic);7 u+ z0 r' r) W6 `* N
  
. `, q+ @1 T2 O# H5 mend hour;7 `- w3 R; d3 R& \/ k
architecture behav of hour is3 o0 N: V! U9 f* V5 l- X9 a
signal clk:std_logic;: g1 b  n, h" B3 a' D4 i4 v1 k
begin
9 `+ B  a3 `4 b* L  U  \9 s    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)! J+ a) N6 n$ w' x: \4 f
     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);$ C2 r5 O; W) }; f8 }2 Q
     variable co1:std_logic;
3 d5 e! [" p! u8 \, A/ r; G     variable co2: std_logic_vector(7 downto 0) ;) m5 W1 v8 H% Y
   begin
# t' l: C' G5 n6 T9 J9 S" {* r    if sig_h="001"and tp_h='1' then clk<=clk_t;
0 t5 f5 G, \9 O4 t3 c   else clk<=clk_h;
' S- P4 J2 I6 f7 ^   end if;
0 o5 p+ J6 }9 R9 ^    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
+ v+ z/ D: H8 e. C3 R. @0 A5 U       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
7 M- u3 k+ d4 c. Z) f. `      if cq1="1010" then cq2:=cq2+1;cq1:="0000";- z9 q7 e  X9 w% P; T9 t5 z: S
            end if;6 b/ S  ?+ h; l, F& d
            if  cq2="0010" and cq1="0100" then! i4 N3 N  u* W1 {
    cq1:="0000";cq2:="0000";& z5 k3 L; u1 K$ s# r% Q7 q
    co1:='1';
/ ^  U! P# i/ c5 p6 v   else co1:='0';
3 |7 L( W/ z# Y      end if;
6 c+ ~- V" H" u2 h; i, z      if cq3="1010" then
  L2 r; |; Q' C  [# O( I      cq4:=cq4+1;
7 X% [# v5 p2 [0 q# Q, m! |7 e+ r      cq3:="0000";# T3 I5 D( V& m3 z/ O. _; @% `/ X
    end if;
. l0 ?' ?1 V; |, L2 ^7 W6 V   if cq4="0001" and cq3="0010" then
3 ]9 X3 P* z. U; s         cq3:="0000";cq4:="0000";co2:=co2+1;
2 v2 f; \8 _5 i8 S- [1 k# W% U2 f      end if;# u5 t, e! V# a+ `
    end if;
/ ]- c; n; \1 Y6 Y/ O* M! I  if hset='1' then    3 m+ e! j' @. u) b$ p0 r! j/ T
          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;& d) K( u: S) v7 H! Y: A
         else) k3 B  E$ w/ F
           if co2(0)='1' then 8 ~# U& [. C. M4 U2 v; i
             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';. I9 K8 j: V# J( }2 l9 {! b5 L+ z
             end if;
' P+ V5 n  Y7 J" N             pm<='1';
6 n$ G8 F1 m/ P            else pm<='0';; J9 C  [* E" x# p
            end if;
, p3 k& h5 c: o% b( L% U            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
$ V+ h; O2 x% V- v2 j, I              else cp_h<='0';  d  [1 \$ v) U* J1 v5 \
             end if;. s( u- `9 Y+ r! q/ W  [. H+ g% v9 V
           din_h1<=cq4;din_h0<=cq3;  
/ X$ F$ }* h6 [7 j' c* A4 M; L/ v        end if;  --12/24转换+ l& \9 @8 f' w/ X+ o' t
  
% i; b9 }3 T' O+ H% l% x     end process;9 R3 v' {, u8 ~
end behav;

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2#
 楼主| 发表于 2009-10-31 17:10 | 只看该作者
报错:" ^( z5 E: ?6 T3 H4 G- x
Info: *******************************************************************
$ S! n, L% K0 bInfo: Running Quartus II Analysis & Synthesis5 ~* Q) {% [8 J& R* L% [) }% u
        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
! w* [* B/ ?+ O" c9 \) V1 y        Info: Processing started: Sat Oct 31 17:04:02 2009& j4 y$ X, ^/ O# i: l
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
1 Z  k  H! ^- z6 _# v, [1 o/ HInfo: Found 2 design units, including 1 entities, in source file hour.vhd3 _) c& h' o$ x
        Info: Found design unit 1: hour-behav0 f, C6 G& {& [8 t+ q
        Info: Found entity 1: hour( }, f2 T3 ~9 c. Y4 \
Info: Elaborating entity "hour" for the top level hierarchy! V. b; l( A/ R- `3 j
Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
( u: e+ w& z% o* z4 Q& [  OWarning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process3 N: K8 w" j# p) K/ ?: C8 [& p; S
Info (10041): Inferred latch for "pm" at hour.vhd(20)3 v0 g4 _6 u  k& Y% [& E7 @
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
' F3 ]) v4 `$ [$ P( w, IError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model5 r, H/ ^7 c: v7 s5 F+ }
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
. H# }5 T  }( c  S+ Q! lError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
; M$ N- ~& J3 E" C- p5 ^Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model, N" m% V2 k$ r# Q' B
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
# B" f# a- }6 [/ ~, FError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model) M' E+ N/ M: s+ l0 {- e, I
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
( ]% k; l# f- y4 b5 z( qError: Can't elaborate top-level user hierarchy: X( q8 S" ~. l- q' c$ O6 f. h4 e
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
/ P4 e- m3 m/ A; P% ]- P2 a; ~' }; n) g        Error: Peak virtual memory: 184 megabytes* U% S9 ^3 ~7 G/ [
        Error: Processing ended: Sat Oct 31 17:04:04 2009  i! g3 d6 N7 s5 p. U
        Error: Elapsed time: 00:00:021 E2 H( b9 v: S3 Y5 A9 L
        Error: Total CPU time (on all processors): 00:00:01, o9 {, v; v3 v1 m( g/ U
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings
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