求救—谁能帮忙改一改

zhong0985

library ieee;
use ieee.std_logic_1164.all;
0 J, G. N! V0 [9 y7 B( Tuse ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
& c& U3 O% t: }8 U* Rentity hour is
port(clk_h,clk_t,tp_h,res_h:in std_logic;
7 |4 U4 C- _1 O7 ^% J' x4 y  hset:in std_logic;
  sig_h:in std_logic_vector(2 downto 0);
8 }( A: |7 v* l6 Y; |7 @6 E0 t# r' y  din_h1ut std_logic_vector(3 downto 0);
; D; [$ I( [2 t" q3 @+ [, J! v  din_h0ut std_logic_vector(3 downto 0);
1 }3 s! D. J$ G, ^: e  pmut std_logic;
  cp_h:out std_logic);
  
. `, q+ @1 T2 O# H5 mend hour;
architecture behav of hour is
signal clk:std_logic;
begin
9 `+ B  a3 `4 b* L  U  \9 s    process(clk_h,clk_t,tp_h,sig_h,res_h,hset)
     variable cq1,cq2,cq3,cq4:std_logic_vector(3 downto 0);
     variable co1:std_logic;
3 d5 e! [" p! u8 \, A/ r; G     variable co2: std_logic_vector(7 downto 0) ;
   begin
# t' l: C' G5 n6 T9 J9 S" {* r    if sig_h="001"and tp_h='1' then clk<=clk_t;
0 t5 f5 G, \9 O4 t3 c   else clk<=clk_h;
' S- P4 J2 I6 f7 ^   end if;
0 o5 p+ J6 }9 R9 ^    if res_h='1' then cq1:="0000";cq2:="0000";cq3:="0000";cq4:="0000";co2:= (OTHERS =>'0');
+ v+ z/ D: H8 e. C3 R. @0 A5 U       elsif  clk'event and clk='0' then cq1:=cq1+1; cq3:=cq3+1;
7 M- u3 k+ d4 c. Z) f. `      if cq1="1010" then cq2:=cq2+1;cq1:="0000";
            end if;
            if  cq2="0010" and cq1="0100" then
    cq1:="0000";cq2:="0000";
    co1:='1';
/ ^  U! P# i/ c5 p6 v   else co1:='0';
3 |7 L( W/ z# Y      end if;
6 c+ ~- V" H" u2 h; i, z      if cq3="1010" then
  L2 r; |; Q' C  [# O( I      cq4:=cq4+1;
7 X% [# v5 p2 [0 q# Q, m! |7 e+ r      cq3:="0000";
    end if;
. l0 ?' ?1 V; |, L2 ^7 W6 V   if cq4="0001" and cq3="0010" then
3 ]9 X3 P* z. U; s         cq3:="0000";cq4:="0000";co2:=co2+1;
2 v2 f; \8 _5 i8 S- [1 k# W% U2 f      end if;
    end if;
/ ]- c; n; \1 Y6 Y/ O* M! I  if hset='1' then   
          din_h1<=cq2;din_h0<=cq1;cp_h<=co1;
         else
           if co2(0)='1' then
             if cq3="0000" and cq4="0000" then cq3:="0010";cq4:="0001";pm<='0';
             end if;
' P+ V5 n  Y7 J" N             pm<='1';
6 n$ G8 F1 m/ P            else pm<='0';
            end if;
, p3 k& h5 c: o% b( L% U            if co2(0)='0' and cq3="0000" and cq4="0000" then cp_h<='1';
$ V+ h; O2 x% V- v2 j, I              else cp_h<='0';
             end if;
           din_h1<=cq4;din_h0<=cq3;  
/ X$ F$ }* h6 [7 j' c* A4 M; L/ v        end if;  --12/24转换
  
% i; b9 }3 T' O+ H% l% x     end process;
end behav;

zhong0985

报错：
Info: *******************************************************************
$ S! n, L% K0 bInfo: Running Quartus II Analysis & Synthesis
        Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
! w* [* B/ ?+ O" c9 \) V1 y        Info: Processing started: Sat Oct 31 17:04:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off hour -c hour
1 Z  k  H! ^- z6 _# v, [1 o/ HInfo: Found 2 design units, including 1 entities, in source file hour.vhd
        Info: Found design unit 1: hour-behav
        Info: Found entity 1: hour
Info: Elaborating entity "hour" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at hour.vhd(29): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
( u: e+ w& z% o* z4 Q& [  OWarning (10631): VHDL Process Statement warning at hour.vhd(20): inferring latch(es) for signal or variable "pm", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "pm" at hour.vhd(20)
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[0]" because its behavior does not match any supported register model
' F3 ]) v4 `$ [$ P( w, IError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[1]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq4[2]" because its behavior does not match any supported register model
. H# }5 T  }( c  S+ Q! lError (10821): HDL error at hour.vhd(48): can't infer register for "cq4[3]" because its behavior does not match any supported register model
; M$ N- ~& J3 E" C- p5 ^Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[0]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[1]" because its behavior does not match any supported register model
# B" f# a- }6 [/ ~, FError (10821): HDL error at hour.vhd(48): can't infer register for "cq3[2]" because its behavior does not match any supported register model
Error (10821): HDL error at hour.vhd(48): can't infer register for "cq3[3]" because its behavior does not match any supported register model
( ]% k; l# f- y4 b5 z( qError: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 2 warnings
/ P4 e- m3 m/ A; P% ]- P2 a; ~' }; n) g        Error: Peak virtual memory: 184 megabytes
        Error: Processing ended: Sat Oct 31 17:04:04 2009
        Error: Elapsed time: 00:00:02
        Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 11 errors, 2 warnings