8片 DDR Layout Guidelines and Topology:

tzwhzf

Layout Guidelines and Topology:
The following are the routing guidelines followed for DDR memory inteRFace section:
$ d/ s0 m/ Y9 F4 }* f% e$ F# [* ?1. Controlled impedance for single ended trace is Z0 = 60 ohm.
6 J, u4 Y3 o" b+ c* L, ~( \2. DQ, strobe, and clock signals are referenced to VSS.
$ B: R& {3 _: S* a2 {# G3. Address, command, and control signals are referenced to VDD.
$ k( k* s* X: c  u, ^' n, B4 S4. The length of address, command, and control signals are matched to clock with +/- 100 mil
tolerance.
5. DQ <0..7> & DM signals are length matched with respect to DQS with +/- 100 mil tolerance
(byte lane).
6. Each byte lanes are routed on same layer.
7. Byte lane to byte lane is matched to clock with +/- 500 mils.
' B5 l% ^$ h  s8. CK & CK# are matched with +/- 30 mil and are routed as diff pair with 120 ohm differential
impedance.
9. Clock - pair to pair matching tolerance is +/- 30 mil.
10. Trace to trace spacing is 2X and signal group to group spacing is 3X.
11. DQS signals are routed in the middle of the byte lane (DQ<0..7>).
: D3 U$ C: b9 _9 ~7 F) I$ I12. Clock trace split point to DRAM is less than 1 inch.
13. VTT and VREF islands are separated with the minimum spacing of 150mils.
14. VTT island width = 150 mil min.; 250 mil preferred.
7 ^7 i, Z& \+ |- s, O15. VREF signal is routed with 20–25 mil minimum trace.
& P  j: D) Y" B/ ]" v& D% p15. All signals are routed with minimum of 3X spacing between other signals
/ m1 I* T" c0 z7 {. K16. Layer biasing is followed for dual strip layers.
6 M5 a. q4 `' v$ K1 ]$ RFigure 1 shows the data bus topology and figure 2 shows the address/control bus topology.

tzwhzf

元件放置方法：

: i/ B$ U2 g# y5 f$ {) i: I  I数据线拓扑：

地址线拓扑：

( P: P+ p; ?$ \2 J( h( w- N时钟线拓扑：
; s7 ]! r6 A& }4 I$ w4 X, U/ v# e

一粒沙

瞄 画个立体的更直观

xieyifu

谢谢楼主，学习了

wanghanq

原档

lbq211

谢谢楼主、楼上的