AGM AG6K(MCU) SoC FPGA

mytomorrow

AGM AG6K(mcu) SoC is targeted to high-volume, cost-sensitive, applications, enabling system designers to meet increasing peRFormance requirements while lowering costs. It is based on AGM SoC architecture. This device integrate one MCU core, AGM programmable logic, 12-bit ADC, 64Mbits SDRAM and 12Mbits SPI NOR FLASH in single device.
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MCU Architecture:
" I/ e$ C; O% U8 x/ H( }. [• One-core MCU: Working frequency up to 250 MHz
• On-Chip Memory: 128Kbytes SRAM
! k& X. o! C# `/ w/ A& G2 s; _* ~• I/O Interfaces:
• External AHB Slave Interface
- p+ ]4 `* G0 g$ K  X9 b5 F• On-Chip Memory Access Ports
; k  x4 l0 k. ]0 A• UART Interface
• GPIOs
• JTAG Debug Ports
• SPI Flash Interface
! }2 Q( P2 q0 c9 B  l) W. Q• Interconnect: ARM AMBA® AHB based
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SDRAM:
• 16bits datawidth
3 i" @9 _' f1 N0 `) o• 64Mbits capability
• up to 166MHz working frequency

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SPI Flash:
& A4 @$ M, X, C. T8 R! L; \2 s• 12Mbits capability
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Analog-to-Digital Converters（ADC）:
• 12bits accuracy
• 1MHz sampling frequency
• On-chip temperature sensing
• Up to 10 channels (include internal temperature sensor channel)

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FPGA Architecture:
& d: R2 ^: s5 G5 M8 y1 V• High-density architecture with 6K LEs
• M9K embedded memory blocks, up to 504 Kbits of RAM space
• Up to 56 18 x 18-bit embedded multipliers are each configurable as two independent 9 x 9-bit multipliers
9 a6 j; _  }6 |. x. \• Provides 4 PLLs per device provide clock multiplication and phase shifting
• High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL
• Support DDR, DDR2
• Single-ended I/O standard support, including 3.3V, 2.5V, 1.8V, and 1.5V LVCMOS and LVTTL
: U, Y+ ^6 k0 Z! U• Flexible device configuration mode: JTAG and AS, PS
; b( }9 X3 ^; ^! h6 r5 v• Support remote update, by “dual-boot” like implementation


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厉害了，英文的