看一下AGM FPGA，pin to pin兼容Altera

mytomorrow

AGM FPGA，pin to pin兼容Altera
1 C5 u: _/ L4 ?4 M, e. @& t国内最好的FPGA，有cpld，FPGA等多种规格器件
5 l% O" K4 w) r8 P! I目前大尺寸LED控制，大屏控制器，小屏驱动器应用领域巨大
' O4 A; ~. v9 O2 Z! D完美兼容Altera
' H& J9 C8 ?7 {5 FEPM240T100系列；EPM570T100系列；EPM576T144系列
EP3C5E144
EP3CE6E22
EP3C5F256
EP4CE6F17
* `3 v2 C/ w/ e3 DEP3C10E144
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7 Z, L0 T+ g; ~+ {0 OEP3C16F256
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AG256 CPLDs is the low cost CPLDs. This instant-on, non-volatile CPLD family targets general-purpose and low-density logic. The logic density is 256 Logic Elements with LQFP-100 package.
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Low-Cost and low-power CPLD
Instant-on, non-volatile standard compatible architecture.
# v; {6 Z5 d- Q( p; vUp to 4 global clock lines in the global clock network that drive throughout the entire device.
Provides programmable fast propagation delay and clock-to-output times.
UFM supports non-volatile storage up to 256 Kbits.
Supports 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic level
/ b# Q# H9 D, _' f' \Programmable slew rate, drive strength, bus-hold, programmable pull-up resistors, open-drain output, Schmitt triggers and programmable input delay.
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry complaint with IEEE Std. 1149.1-1990
3 T, A5 }' W, |4 Q  T2 L1 IISP circuitry compliant with IEEE Std. 1532
3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS and LVTTL standards
Emulated LVDS output (LVDS_E_3R)
Emulated RSDS output (RSDS_E_3R)



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