FPGA --- Verilog基础知识（有符号数运算规则，加减运算，乘法运算中的符号位拓展...

thinkfunny

rule of thumb
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• The format of the signed type is two’s complement. 有符号数均为补码表示
• If any operand in an expression is unsigned the operation is considered to be unsigned. 只有计算表达式右边有无符号数，整个计算式都按照无符号数规则运算
• 只有算式右边全为有符号数，运算才会自动补齐所需的bit数，n+n=n+1.n*n=2n
• The value -4 represented as a 3bit signed hex value would be specified as -3’sh4. A decimal number is always signed. verilog2001中用’s来特别声明有符号数，十进制的数都是有符号数
• Type casting using $unsigned will make the operation unsigned. The operand will be sign extended with 0’s if necessary. $usigned()函数在高位补0
• A=$signed(B) will extend using sign bit. $unsigned()函数会在高位补与符号位相同的bit
  

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: O$ x$ t  ^: i: q5 N' ?* X0 ~4 Ybasic signed addition


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wu68aq

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