关于FPGA的DS18B20模块的时序问题，感觉一点错都没有啊...

littlestupid

求大神指导一下到底哪里错了，已经调试了三四天了，不管怎么调temp的值都是0.。。

module DS18B20
0 V$ @# y+ a4 Q3 P( r8 D(
" _9 B" Q0 K. I  E* @CLK48M,
! b1 Z3 q  f6 B//RST,
7 w6 e' _+ o  aDQ,
temp
7 X3 {3 k( [* t. u$ P; X, [# I);
//Port declaration
input CLK48M;
//input RST;
  v& e6 |6 D, vinout DQ;
output [11:0] temp;

reg [7:0] Cnt;
reg clk1MHz;

always@(posedge CLK48M)
begin
if(Cnt==8'd23)
( m2 y4 N* \) K7 @8 a  k0 rbegin
2 l! _- a6 V1 xCnt<=8'd0;
clk1MHz<=~clk1MHz;
end
% B3 Y" [7 U4 n9 D+ [else
Cnt<=Cnt+8'd1;
end

parameter IDLE = 11'b000_0000_0001,
DO_RESET = 11'b000_0000_0010,
. p7 u& R5 D: v3 X, o, f3 W) }; s" hCMD_CC = 11'b000_0000_0100,
CMD_44 = 11'b000_0000_1000,
1 l$ Z, Q1 x3 A3 @CMD_BE = 11'b000_0001_0000,
) W: g3 ~. V9 [5 ]WRITE_BYTE = 11'b000_0010_0000,
7 P; y! |; @4 }' C+ \/ lWrite_High = 11'b000_0100_0000,
. I1 o1 l. S  P6 V. \Write_Low = 11'b000_1000_0000,
WAIT_750ms = 11'b001_0000_0000,
' ?- M# C& M  X! P0 M4 f9 k  VREAD_BIT = 11'b010_0000_0000,
GET_TMP = 11'b100_0000_0000,
WAIT_4MS = 11'b100_1000_1000;
//-------------------------------------------------------------------
reg [10:0] state;
* v  y8 O" H7 Q- B$ b% Creg [31:0] counter;
reg DQ;
reg [7:0] write_byte;//中间寄存器,保存主机要写的指令字节
) c% ?3 N5 |8 f0 P  J$ m5 Lreg [3:0] write_byte_cnt;
1 q+ x% m& }6 E4 mreg [1:0] byte_flag;
reg [3:0] read_bit;
5 R: Q6 \; j/ F/ x. Freg[11:0] temp;//12位温度数据
reg TMP_bit;

always@(posedge clk1MHz)
begin
case(state)
IDLE:
begin
DQ<=1'bz;//空闲状态释放数据总线,由外接上拉电阻将DQ数据线置高
counter<=0;
write_byte_cnt<=4'b0000;
8 y9 O( F2 F% ~byte_flag<=2'b00;
8 u4 s6 l% D0 H/ {$ g  `read_bit<=4'b0;
state<=DO_RESET;
4 Y% D' I  e2 ^end
DO_RESET://主机拉低数据总线持续至少480us，然后释放总线
% V' J" s7 u5 G4 V( a1 hbegin
( W6 F- ]) e" {1 l2 Tif(counter<=480)
begin
DQ<=1'b0;//拉低数据线480us
counter<=counter+1'b1;
end
" N9 x, O5 [9 Z1 V* }5 u3 |else if(counter>480 && counter<=780)
9 r% z& m; o! L* Vbegin
4 s4 L/ U; ?+ F' O# A. ]- RDQ<=1'bz;//释放数据总线60us+240us=300us
counter<=counter+1'b1;
* T! T" v1 N# m: {* S# ~4 V( A9 Pif(DQ)//检测从机是否发送Presence Pulse(持续60us~240us低电平)
( ^: p9 w" y( G, H3 c, r+ D/ zbegin
state<=CMD_CC;
, c$ ]1 Y5 D( @$ R' ^" S. lcounter<=0;
end
% i+ R  ^/ Z  ?else
begin
: L7 S* \; @, J2 H1 N1 @9 mstate<=IDLE;
end
9 I& D: e; F2 y# D, ~' tend
end
7 g+ E: E; [6 P4 dCMD_CC:
' Z% h/ ], B& `8 cbegin
  s; N! A' z; U7 U& g4 ]write_byte<=8'hCC;
state<=WRITE_BYTE;
# h4 f7 n' w, x: w% b" e# fend
WRITE_BYTE://写指令字节,由低位向高位依次写入从机
; ^6 G- f, K" {  Y7 R7 vbegin
case(write_byte_cnt)
4'b0000:
# u8 H8 g: k% S  P; ?# Ebegin
state<=write_byte[0]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
end
% F  `6 p5 Z& |* k' l5 Q9 \: ^6 F4'b0001:
2 G, `8 p) `% O+ {% J: mbegin
state<=write_byte[1]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
  W4 q# Q6 n+ w5 I) hend
' g, `8 k+ ]1 I* V/ Y2 d' F% D( ~) F4'b0010:
begin
state<=write_byte[2]?Write_High:Write_Low;
+ l8 U- G; B! E( w. M7 v- iwrite_byte_cnt<=write_byte_cnt+1'b1;
end
" H9 E4 o; ?# I; r, i! A4 @4'b0011:
/ b4 r  Q7 \/ Q9 t* Z4 wbegin
% ^8 c; f) M# \) e3 j: \state<=write_byte[3]?Write_High:Write_Low;
' p! i8 L: ]( Z! }. [( f! Swrite_byte_cnt<=write_byte_cnt+1'b1;
end
( O) D# T" B; p6 [8 ^) F4 g% c+ T4'b0100:
begin
state<=write_byte[4]?Write_High:Write_Low;
5 f& e: h" l( @* u) Owrite_byte_cnt<=write_byte_cnt+1'b1;
end
" m3 Z3 E% i) i1 C8 g4'b0101:
begin
state<=write_byte[5]?Write_High:Write_Low;
  B4 N7 w# Y, ]8 X3 A& Ywrite_byte_cnt<=write_byte_cnt+1'b1;
# y& X5 z6 @  c, J. cend
4'b0110:
6 L+ o+ f) _" [, |" |, vbegin
+ k' l3 P; @# _% [; Bstate<=write_byte[6]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
end
/ ?- p3 Q" {& l: t4'b0111:
9 P5 M( p' l4 |begin
: u: T7 O9 I/ h5 S  d" kstate<=write_byte[7]?Write_High:Write_Low;
write_byte_cnt<=write_byte_cnt+1'b1;
% B# w% g1 ]; G1 j) `end
4 r4 z) S1 @2 p" U9 \# L4'b1000://8bit字节写完后在此处进行状态转换
: l! o5 [7 \9 n; Qbegin
write_byte_cnt<=4'b0000;
case(byte_flag)
2'b00:
: Y% F% W6 Y+ @5 b  r3 O( ^begin
state<=CMD_44;
) `. }! e/ \9 T! N, X2 kbyte_flag<=2'b01;
5 a7 r2 M* E& U+ N5 Nend
' l9 l! }: C- h7 |* e7 m2'b01:
+ V8 g0 j( x7 x$ _! rbegin
state<=DO_RESET;
- ?: Y  e, v; \: Dbyte_flag<=2'b10;
end
5 F2 q% u3 z/ r2'b10:
begin
) m+ B/ H# P2 x9 H* ]/ |! Cstate<=CMD_BE;
) n2 F9 X5 P8 [; @* ]  ^byte_flag<=2'b11;
3 Q0 I) X2 v* U- v5 N& T, Nend
2'b11:
begin
0 T! ]6 }: p$ Q  s  {state<=GET_TMP;
6 g0 r( p% y6 I  ]$ H( e+ ^. ubyte_flag<=2'b00;
end
endcase
9 K: J( p$ e3 Q, R: D/ S* Z! kend
6 t( z% C7 M2 j4 x. k( |8 pdefault:write_byte_cnt<=4'b0000;
endcase
end
Write_High://写‘1’时序:主机拉低数据线1~27us,然后释放数据总线30~数千us.
begin
$ u0 _$ s3 |2 I0 H$ Mif(counter<=8)//拉低数据线15us(至少1us)
begin
1 L/ V- X6 L1 K1 |) v% U0 S. {2 qDQ<=1'b0;
counter<=counter+1'b1;
6 [0 B8 A- F( P: C3 a4 N8 Q1 l' Cend
else if(counter>8 && counter begin
* ?) [) a* K' m- _1 N4 [DQ counter end
else
begin
' f. ~$ u6 Y7 g$ [, E. i, icounter state end
end
Write_Low://写‘0’时序:主机拉低数据线30~227us,然后释放数据总线1us~数千us.
. L8 V& _" |( kbegin
. b% ]* n$ y# V8 z% `if(counter begin
0 A" F3 v7 V4 H. q3 O4 g9 u  NDQ counter end
$ t: }( k$ p8 `else if(counter>78 && counter begin
DQ counter end
else
0 A, p& j) r* G$ a" }6 U. I1 J1 Nbegin
counter state end
- m$ k% y  B9 L) hend
CMD_44:
, g( b) p0 M! q* S0 r6 Bbegin
6 X. G' V2 e6 P+ v$ owrite_byte state end
( ]9 z7 u: ~# ?! n& S+ f5 S3 D0 lWAIT_750ms:
# S1 Q4 e  E; Ebegin
if(counter>750000)//实际上只等待几us甚至不等待也可以
- H! E% {# k* qbegin
state<=DO_RESET;
counter<=0;
end
else
counter<=counter+1'b1;
end
CMD_BE:
2 w# S3 k- r$ y+ @& a8 Ebegin
  S. T: B( h- G* n( U6 Wwrite_byte<=8'hBE;
state<=WRITE_BYTE;
end
( i  g: h9 {+ Y% sGET_TMP:
- j# I/ l1 m' ~. \begin
7 N. H9 L5 c. M" y% @case(read_bit)
" B' H( j- ~; `9 E( K2 }5 y$ @4'h0:
5 I, O& {" e" J; ?- q3 Q* E- I" x4 r! Wbegin
state<=READ_BIT;
: ^0 f% p" A! F4 Jread_bit<=read_bit+1'b1;
end
0 V4 T) j' a$ E: y4'h1:
1 I/ j# _' t9 e' Fbegin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
0 ~9 n6 \+ b0 `# g0 Y: h/ ]2 t2 X" Xtemp[0]<=TMP_bit;
. J& t$ Q5 a+ J- send
" b7 B3 E0 z( P$ g9 S$ I4'h2:
* Y, e. S2 A0 d: q4 T$ Xbegin
state<=READ_BIT;
9 L: [: }9 u3 B7 a6 Z* kread_bit<=read_bit+1'b1;
temp[1]<=TMP_bit;
" L2 i8 Y. Z7 }6 V, S0 X2 |, f% Kend
4 D9 d$ b0 D7 D# F! v- `! Q8 t4'h3:
begin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
# t4 G4 X% a' h2 jtemp[2]<=TMP_bit;
6 w1 W* X$ w$ ^5 P7 g" ]end
# O& e( Y6 `0 I0 {- m/ G& g" d8 R4'h4:
' \) `" W8 c( V% Y" H& wbegin
state<=READ_BIT;
5 j1 U( f+ C0 jread_bit<=read_bit+1'b1;
temp[3]<=TMP_bit;
end
+ _4 Q% z' V, G9 B4'h5:
begin
3 j- X( m: c& e6 u6 s7 Lstate<=READ_BIT;
read_bit<=read_bit+1'b1;
" n7 U' k! r/ I+ z/ F' @temp[4]<=TMP_bit;
end
4'h6:
/ A/ w4 k$ z9 F8 U2 |1 bbegin
0 D! G7 U& p+ q: l& @9 Sstate<=READ_BIT;
- C9 ^& ~' w. B* \/ `8 H5 ~0 [read_bit<=read_bit+1'b1;
temp[5]<=TMP_bit;
0 @3 Y3 C9 n* hend
9 s, A7 P: N0 g# u" `4'h7:
begin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
temp[6]<=TMP_bit;
end
% J# g0 O9 j" |# n# p% G- V4'h8:
* ^$ t9 N0 S* {3 E' Ibegin
) p4 c3 g) F: |4 Y/ k4 Kstate<=READ_BIT;
2 r9 }7 m% {8 Xread_bit<=read_bit+1'b1;
temp[7]<=TMP_bit;
7 R& r( f- }2 e& `& e( }  Fend
4'h9:
% }8 S, f: I! Hbegin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
0 \5 V" V5 }$ ^, v) S: _8 ttemp[8]<=TMP_bit;
end
7 n* h% v( x+ y9 L, S, i* T( i4'hA:
begin
state<=READ_BIT;
read_bit<=read_bit+1'b1;
: V7 H0 l) v' q1 {temp[9]<=TMP_bit;
end
* `" v: W" @9 \6 h- f5 W4'hB:
begin
6 s% i* J/ d* A, Y1 }state<=READ_BIT;
read_bit<=read_bit+1'b1;
temp[10]<=TMP_bit;
6 C! a# ~" J: W  f9 Tend
- D  c, k, ^0 `" S4'hC:
begin
state<=WAIT_4MS;
read_bit<=4'h0;
temp[11]<=TMP_bit;
end
default:read_bit<=4'h0;
endcase
end
. S& R5 z+ e; N' ]  jREAD_BIT://读时序:主机拉低数据总线约2~4us,然后释放数据总线2~4us,再读取DQ数据线上的值
: Z' {# x: G# c: ^* W: l8 n9 nbegin
if(counter>=0 && counter<=3)
begin
2 F2 c; Z9 N' ]( a; vDQ<=1'b0;//主机拉低数据总线约5us
counter<=counter+1'b1;
( e# z. T* C, ?# A" Dend
else if(counter>=4 && counter<=7)//最迟必须在29us处释放数据线
( Q. g0 G4 c  G' ^begin
DQ<=1'bz;//释放数据总线5us
counter<=counter+1'b1;
6 f, b) J7 }* s0 zend
% P% _" F8 j- I1 Y. T/ e& jelse if(counter==8)
begin
+ X8 z# Z2 R# I* ?
counter<=counter+1'b1;
8 E8 b5 n& t3 b1 p% B2 n9 }" ]& cTMP_bit<=DQ;
end
else if(counter>=9 && counter begin
counter end
2 |. ?& }: \5 l; x% Eelse
/ l0 W: J+ s5 g) {+ J% `" ]begin
# u6 I) M( i; h9 \state counter end
end
8 y& g, {6 j3 b) Y" g, A* N. d" HWAIT_4MS:
& G1 ~% p. N' X8 Dbegin
if(counter>4000)
begin
state<=IDLE;
0 N6 l) j/ s: N# G% v1 Z3 ]counter<=0;
end
( \) H/ S9 n5 p$ f: }* N! o3 delse
begin
/ h2 i$ H, i5 _counter<=counter+1'b1;
end
* ^- H  P& K# i2 O! Z0 v1 Nend
/ Z+ X6 @/ M; t( _default:state<=IDLE;
/ a* g( Z$ \0 O# V4 jendcase

end
endmodule

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