FPGA cyclone3代芯片，利用lvds_rx IP核进行LVDS信号采集出现问题

smileqq

在Quartus软件里进行Pin Planner设置出现了以下错误提示：
希望各位大神能帮忙解答！
错误提示1：
Error: The input pin RX_IN has I/O standard LVDS_E_3R, but the selected device does not support input pin operation with I/O standard LVDS_E_3R

错误提示2：
( v5 k) ]$ l# N; W) h6 K# V0 TError: Pad 106 of non-differential I/O pin 'RX_IN1[2]' in pin location AB5 is too close to pad 105 of differential I/O pin 'RX_IN1[3]' in pin location AB6  --  pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug.

楼主初级入门，不太明白。因为检查了cyclone3的引脚表，都是支持差分IO的  但是在软件里设置就老出问题。

/ {' G# b# N) T0 ]

wu68aq

同问