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关于VHDL按键去抖如何实现 按键检测需要消抖,一般有硬件和软件两种方式。硬件就是加去抖动电路,这样从根本上解决按键抖动问题。除了用专用电路以外,用可编程FPGA或者cpld设计相应的逻辑和时序电路,对按键信号进行处理,同样可以达到去抖动的目的。
x( V7 g" U, z 本例中用状态机实现了消抖电路:
+ \" j1 f- O" L7 c, k4 y1 u端口描述:clk 输入检测时钟;reset 复位信号;din 原始按键信号输入; dout 去抖动输出信号。8 k# {9 e+ a1 U0 M6 r. y& k3 K; u( U
8 c% S: I1 y. [
VHDL源码如下:
. L& h0 o# m0 o2 g! T6 \, e6 XLIBRARY ieee;6 N+ N7 l8 R; n% O
USE ieee.std_logic_1164.all;
# S5 O9 _' w) F" b; g1 d6 iUSE ieee.std_logic_unsigned.all;
: N7 Z: i' A# K% {; _# |ENTITY xiaod IS# I3 ^( O' z+ `! R8 F) u
PORT0 ?) f! \0 X7 [
(/ ]( K6 Z: @/ T# o
clk : IN STD_LOGIC ;* J: z3 [* j1 t+ G' M
reset : IN STD_LOGIC ;( T U, k% ~# O! u& _
din : IN STD_LOGIC ;
* C6 H1 Y! M0 m4 G y* E dout : OUT STD_LOGIC
. p" e4 p+ c$ y v5 r2 I j);
+ S, R! X- [9 ^1 o1 A O4 M& ?3 REND ENTITY;
1 Q; `& F% B5 Q# Z0 d3 A3 YARCHITECTURE RTL OF xiaod IS$ S$ V3 P. e/ c/ ]4 k* k7 k
TYPE state IS( s0,s1,s2,s3);
* o8 L( J/ x3 N( g, |SIGNAL pre_s, next_s: state;
1 `. V7 C" R, C& a) G7 [BEGIN
0 e) I1 m( A' j( m3 J& S
% @' l: m. i4 H7 M% B8 VP0 ROCESS( reset, clk )& I# ~$ u5 q' R1 H. d
BEGIN
$ a# a- A1 Y6 K* } if reset = '0' then
0 d0 Q5 E: e6 o d2 i: E pre_s <= s0;' L+ X* H4 }9 i% N. ]
elsif rising_edge( clk ) then
& ~/ c0 e6 v6 Y- G2 \ pre_s <= next_s;3 Y- |7 E/ I6 R! V4 w' {' e) f
else! U2 H3 B* V1 ]! v, Q# v
null;$ E5 n2 y$ r5 p$ o4 [% W4 {# C
end if;' W+ l. ^0 W: _5 a# n2 G- t6 |% M
END PROCESS P0;
' N/ T- `% O* X8 u- I! D7 R
, u L( M9 _, ?- X: rP1 ROCESS( pre_s, next_s, din )
. H$ y. _4 N$ X: KBEGIN4 ]7 B( `- Y: j: u$ |- U
case pre_s is
$ j- h: Z! ]1 E/ y
" o* u P) J. C( `5 ] when s0 =>
* U& Y7 M w5 _$ E0 k ]& S" O dout <= '1';
- i: A4 n4 G6 Q) _4 Z if din = '1' then 5 T3 z, Q Y; G# G: M; X1 v* g; v
next_s <= s0;; ]4 l' a6 E; y) B1 B: \& p
else6 V- Y+ t, N3 o
next_s <= s1;
! K4 S8 R# x5 C2 D) _6 P7 }3 n end if;
8 l- Q; ?# {+ \- V
: R- _4 u. \6 z; O# H( ? Y8 k* G when s1 =>5 Q" F! ]. z. {' Y/ \+ {
dout <= '1';
5 e+ b) t8 y' C if din = '1' then
$ S1 L1 W5 ]5 H5 Z next_s <= s0;
( y0 V% d) ?' e4 p3 J$ _, \+ R7 ?5 T& O else
5 ~. r4 }+ Z1 E3 y next_s <= s2;: K0 S5 C3 i1 U8 ?+ s% V# F
end if;/ x% Z, F F- t; N, @3 v1 G7 S
s8 R* A; D* N4 m when s2 =>0 `5 M* G# U$ |1 \" ]+ H
dout <= '1';
- W2 M0 L I7 l* { ] t if din = '1' then
" C% Y9 K0 ?& X' V! O- @; F9 u next_s <= s0;: ]1 {$ O6 m7 }1 m+ [. m* ]
else) L4 \( d+ Y/ f$ ~
next_s <= s3;+ l! V0 B5 U4 j
end if; 6 V$ ?& H8 y- d# v
) h( D1 t- }9 r: T! P/ T. M when s3 =>; G& I9 e3 G# D+ c; V8 s
dout <= '0';% v) z- I9 ]5 g3 D( o* ~' Q
if din = '1' then
- @3 r3 O/ c) R; g: k# {6 D8 |" L next_s <= s0;
/ w+ F- e& c! s& R6 P else
; p! m7 R: S8 ]+ p% S$ A next_s <= s1;
( C! N+ ]+ x# }4 K# w5 Y% B end if;& q+ c0 z3 B8 O" X6 u% O+ L+ F
end case;
! R/ |1 C: Y- Q3 M: m' y7 \% y, ~8 {6 @: s4 e! V
END PROCESS P1;
7 o7 b, W# J7 l2 i9 F# ~& qEND RTL; / |! |! `7 i& f4 r
多按键去抖动电路VHDL源码,按键个数参数化,每个按键处理调用了上面的模块:
+ ~" q8 B) i7 T2 `8 V- _6 {2 H" n8 N9 B# v/ ?. v; E0 B* z. Y6 {
LIBRARY ieee;
* S% b* V. U0 ?USE ieee.std_logic_1164.all;2 u% l) D# V! r9 L
USE ieee.std_logic_arith.all;
6 D6 S" o* q3 g& wUSE ieee.std_logic_unsigned.all;* ?$ E- Z; K& U$ D& G, D$ N# x
ENTITY Nxiaod IS A, n; R, f* i- @6 `/ K# u$ R
GENERIC( width: positive:= 5 );
: [+ S, \5 K# h' y* G, m
; R3 q+ C) L2 O1 [3 KPORT
9 g* n& p: _) f! D' \(* k$ U' q, I# k
clk : IN STD_LOGIC ;7 C% X% Q: I: ^3 w
reset : IN STD_LOGIC ;
% y4 f: D- X4 G+ I) K din : IN STD_LOGIC_VECTOR( width - 1 DOWNTO 0);
6 H% ~$ e+ H0 h/ x dout : OUT STD_LOGIC_VECTOR( width - 1 DOWNTO 0)
$ I7 p6 s) M b9 o% x2 q);
% ~* F0 N6 p4 W9 `7 P9 TEND ENTITY;1 s; N4 p6 o% ] f. q* |; G
ARCHITECTURE RTL OF Nxiaod IS! y+ [: P! d7 ^- [
/ v4 @" V+ _8 Y% U; `: J% ^COMPONENT xiaod IS: S5 ^3 L6 x1 J7 N
PORT
2 J! Q: P2 _% P: Z% J, A(7 f% f6 p0 Q6 Y7 f) P7 Q. x- ]
clk : IN STD_LOGIC ;
: g6 D; }# U9 }% q$ B+ j' b1 h4 A reset : IN STD_LOGIC ;
$ w: O x/ u/ y5 ^# r; d din : IN STD_LOGIC ;/ A- o* s6 l2 w8 t' c' o" a4 `8 R
dout : OUT STD_LOGIC
0 W# o; w2 J0 n9 s, o* {);
5 L! v! [" G' V0 [" }END COMPONENT;" x) g! `6 H4 j. X' _' Q
BEGIN4 @$ @6 @, L* t9 o4 t! s
g1: FOR i IN 0 to width - 1 GENERATE
# j/ q2 R. O- f9 n" @. H" ^ux: xiaod port map( clk => clk, reset => reset, din => din(i), dout => dout(i));
1 p5 O: j* W+ h$ Q) nEND GENERATE;% k* f* o. F6 s b* i
END RTL;
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