EDA实验与实践 dds_test

A-Lin · 发表于 2019-5-8 09:36

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EDA实验与实践 dds_test

module dds_test(clock,key,fword,seg,dig);
input clock;                         //系统时钟(48MHz)
input[7:0] key;                         //按键输入(KEY1~KEY5)
output[31:0]fword;                      //要发送的数据
output[7:0]seg;                         //数码管段码输出
output[7:0]dig;                         //数码管位码输出
//I/O寄存器
reg[31:0]fword;
reg[7:0]seg;
reg[7:0]dig;
//内部寄存器
reg[16:0]count;                         //时钟分频计数器
reg[7:0]dout1,dout2,dout3;             //消抖寄存器
reg[7:0]buff;                         //边沿检测寄存器
reg[2:0] cnt;                            //数码管扫描计数器
reg[3:0]disp_dat;                      //数码管扫描显存
reg div_clk;                         //分频时钟
wire[7:0] key_edge;

//时钟分频部分
always @(posedge clock)
begin
if (count < 17'd120000)
begin
      count <= count + 1'b1;
      div_clk <= 1'b0;
   end
   else
   begin
      count <= 17'd0;
      div_clk <= 1'b1;
   end
end

//按键消抖部分
always @(posedge clock)
begin
if(div_clk)
begin
      dout1 <= key;
      dout2 <= dout1;
      dout3 <= dout2;
end
end

//按键边沿检测部分
always @(posedge clock)
begin
buff <= dout1 | dout2 | dout3;
end

assign key_edge = ~(dout1 | dout2 | dout3) & buff;

always @(posedge clock)                         //按键1
begin
if(key_edge[0])                               //下降沿检测
fword[31:28] <= fword[31:28] + 1'b1;
end

always @(posedge clock)                         //按键2
begin
if(key_edge[1])                               //下降沿检测
fword[27:24] <= fword[27:24] + 1'b1;
end

always @(posedge clock)                         //按键3
begin
if(key_edge[2])                               //下降沿检测
fword[23:20] <= fword[23:20] + 1'b1;
end

always @(posedge clock)                         //按键4
begin
if(key_edge[3])                               //下降沿检测
fword[19:16] <= fword[19:16] + 1'b1;
end

always @(posedge clock)                         //按键5
begin
if(key_edge[4])                               //下降沿检测
fword[15:12] <= fword[15:12] + 1'b1;
end

always @(posedge clock)                         //按键6
begin
if(key_edge[5])                               //下降沿检测
fword[11:8] <= fword[11:8] + 1'b1;
end

always @(posedge clock)                         //按键7
begin
if(key_edge[6])                               //下降沿检测
fword[7:4] <= fword[7:4] + 1'b1;
end

always @(posedge clock)                         //按键8
begin
if(key_edge[7])                               //下降沿检测
fword[3:0] <= fword[3:0] + 1'b1;
end

//数码管扫描显示部分
always @(posedge clock)                //定义上升沿触发进程
begin
if(div_clk)
      cnt <= cnt + 1'b1;
end

always @(posedge clock)
begin
if(div_clk)
begin
      case(cnt)                         //选择扫描显示数据
         3'd0:disp_dat = fword[31:28]; //第一个数码管
         3'd1:disp_dat = fword[27:24]; //第二个数码管
         3'd2:disp_dat = fword[23:20]; //第三个数码管
         3'd3:disp_dat = fword[19:16]; //第四个数码管
         3'd4:disp_dat = fword[15:12]; //第五个数码管
         3'd5:disp_dat = fword[11:8]; //第六个数码管
         3'd6:disp_dat = fword[7:4];       //第七个数码管
         3'd7:disp_dat = fword[3:0];       //第八个数码管
      endcase
      case(cnt)                         //选择数码管显示位
         3'd0:dig = 8'b01111111;          //选择第一个数码管显示
         3'd1:dig = 8'b10111111;          //选择第二个数码管显示
         3'd2:dig = 8'b11011111;          //选择第三个数码管显示
         3'd3:dig = 8'b11101111;          //选择第四个数码管显示
         3'd4:dig = 8'b11110111;          //选择第五个数码管显示
         3'd5:dig = 8'b11111011;          //选择第六个数码管显示
         3'd6:dig = 8'b11111101;          //选择第七个数码管显示
         3'd7:dig = 8'b11111110;          //选择第八个数码管显示
      endcase
end
end

always @(disp_dat)
begin
case(disp_dat)                      //七段译码
      4'h0:seg = 8'hc0;             //显示0
      4'h1:seg = 8'hf9;             //显示1
      4'h2:seg = 8'ha4;             //显示2
      4'h3:seg = 8'hb0;             //显示3
      4'h4:seg = 8'h99;             //显示4
      4'h5:seg = 8'h92;             //显示5
      4'h6:seg = 8'h82;             //显示6
      4'h7:seg = 8'hf8;             //显示7
      4'h8:seg = 8'h80;             //显示8
      4'h9:seg = 8'h90;             //显示9
      4'ha:seg = 8'h88;             //显示a
      4'hb:seg = 8'h83;             //显示b
      4'hc:seg = 8'hc6;             //显示c
      4'hd:seg = 8'ha1;             //显示d
      4'he:seg = 8'h86;             //显示e
      4'hf:seg = 8'h8e;             //显示f
endcase
end

endmodule

Demyar · 发表于 2019-5-8 18:02

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EDA实验与实践 dds_test

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